A system verification strategy based on the BST infrastructure

A good verification strategy should bring near the simulation and real functioning environments. In this paper we describe a system-level co-verification strategy that uses a common flow for functional simulation, timing simulation and functional debug. This last step requires using a BST infrastruc...

Full description

Saved in:
Bibliographic Details
Main Authors: Alves, G.R., Ferreira, J.M.M.
Format: Conference Proceeding
Language:English
Subjects:
Binary search trees
Clocks
Control systems
Field programmable gate arrays
Hardware
Logic testing
Pins
Process control
Prototypes
Timing
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A good verification strategy should bring near the simulation and real functioning environments. In this paper we describe a system-level co-verification strategy that uses a common flow for functional simulation, timing simulation and functional debug. This last step requires using a BST infrastructure, now widely available on commercial devices, specially on FPGAs with medium/large pin-counts.
DOI:10.1109/ISCAS.1999.777799