PARC: a new pyramidal FPGA architecture based on a RISC processor

This paper presents a new pyramidal architecture FPGA intended for fast dynamic configurations (PARC) and highly efficient medium design implementation. This device consists of a large number of fine-grained arrays of optimized heterogeneous logic blocks and a new pyramidal structure with three hier...

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Bibliographic Details
Main Authors: Rabel, C.E., Sawan, M.
Format: Conference Proceeding
Language:English
Subjects:
Acceleration
Automatic control
BiCMOS integrated circuits
Design automation
Field programmable gate arrays
Logic arrays
Logic devices
Random access memory
Reduced instruction set computing
Routing
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Summary:This paper presents a new pyramidal architecture FPGA intended for fast dynamic configurations (PARC) and highly efficient medium design implementation. This device consists of a large number of fine-grained arrays of optimized heterogeneous logic blocks and a new pyramidal structure with three hierarchical levels. In addition, either logic blocks and/or I/O blocks are simplified in order to highly accelerate the routing process which is performed by a controller. The PARC device is a reprogrammable SRAM based product developed with Synopsys design automation CAD tools, using VHDL and the 0.8 /spl mu/m BiCMOS cell library from Nortel, to operate at a 50 MHz clock frequency. These various features allow for very fast routing-speed improvement when compared to the XC4003A from Xilinx company.
DOI:10.1109/ISCAS.1999.777927