A 2.25-2.7 GHz Area-Efficient Subharmonically Injection-Locked Fractional-N Frequency Synthesizer With a Fast-Converging Correlation Loop

• Published in: IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2017-04, Vol.64 (4), p.811-822
• Main Authors: Tseng, Yen-Hsiang, Yeh, Che-Wei, Liu, Shen-Iuan
• Format: Article
• Language: English
• Subjects: Capacitors; Convergence; Converters; Correlation; Correlation loop; correlator; Delays; digital-to-time converter (DTC); fractional-N; Frequency locking; frequency synthesizer; Frequency synthesizers; Microprocessors; Phase locked loops; Phase noise; phase-locked loop (PLL); Power consumption; Search algorithms; subharmonically injection-locked technique; Synthesis; Transfer functions; Voltage-controlled oscillators
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2016.2620151

An area-efficient subharmonically injection-locked fractional-N frequency synthesizer is presented. The phase domain analysis confirms that a second-order subharmonically injection-locked phase-locked loop (SIPLL) can be stable even if the loop filter is composed of only a tiny capacitor. Thus, the area of the loop filter shrinks dramatically to realize an area efficient SIPLL. Besides, a fast-converging correlation loop is used to calibrate the gain error of the digital-to-time converter in background by using a binary search algorithm. It ensures the initial output of the correlator close to the final one and is insensitive to process/supply/temperature variations. The chip is fabricated in a 40 nm process and occupies a core area of 0.0104 mm 2 . The converging time of the correlation loop is within 30 μs. The power consumption is 3.19 mW from a 1.1 V supply.