Resource-Efficient SRAM-Based Ternary Content Addressable Memory

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2017-04, Vol.25 (4), p.1583-1587
• Main Authors: Ahmed, Ali, Kyungbae Park, Sanghyeon Baeg
• Format: Article
• Language: English
• Subjects: Artificial intelligence; Associative memory; Emulation; Field programmable gate arrays; Field-programmable gate array (FPGA); Memory architecture; memory–throughput tradeoff; Random access memory; SRAM-based ternary content addressable memory (TCAM); static random access memory (SRAM); Throughput
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2016.2636294

Static random access memory (SRAM)-based ternary content addressable memory (TCAM) offers TCAM functionality by emulating it with SRAM. However, this emulation suffers from reduced memory efficiency while mapping the TCAM table on SRAM units. This is due to the limited capacity of the physical addresses in the SRAM unit. This brief offers a novel memory architecture called a resource-efficient SRAM-based TCAM (REST), which emulates TCAM functionality using optimal resources. The SRAM unit is divided into multiple virtual blocks to store the address information presented in the TCAM table. This approach virtually increases the overall address space of the SRAM unit, mapping a greater portion of the TCAM table in SRAM and increasing the overall emulated TCAM bits/SRAM at the cost of reduced throughput. A 72 × 28-bit REST consumes only one 36-kbit SRAM and a few distributed RAMs via implementation on a Xilinx Kintex-7 field-programmable gate array. It uses only 3.5% of the memory resources compared with a conventional SRAM-based TCAM (hybrid-partitioned TCAM).