Layer assignment for maximizing the reliability of 3D ICs

In the design of a three-dimensional integrated circuit (3D IC), the task of layer assignment is to assign each functional unit to a layer that can accommodate it. In a 3D IC, through silicon vias (TSVs) are used to communicate signals between different layers. To improve the reliability of a 3D-IC,...

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Bibliographic Details
Main Authors: Jing-Ren Chen, An-Jie Shih, Chun-Wei Lee, Chun-Hua Cheng, Shih-Hsu Huang
Format: Conference Proceeding
Language:English
Subjects:
Integrated circuit reliability
Linear programming
Reliability engineering
Three-dimensional displays
Through-silicon vias
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Summary:In the design of a three-dimensional integrated circuit (3D IC), the task of layer assignment is to assign each functional unit to a layer that can accommodate it. In a 3D IC, through silicon vias (TSVs) are used to communicate signals between different layers. To improve the reliability of a 3D-IC, previous layer assignment works concentrate on minimizing the number of TSVs to reduce the risk of the defect occurred in the manufacturing process. However, the risk in the fabricating process of a TSV is also related to the length of this TSV. Based on this observation, in this paper, we propose an integer linear programming (ILP) approach to maximize the reliability of TSVs during the layer assignment stage. Compared with the previous work (that does not take the reliability of TSVs into account), experimental results show that our approach can greatly increase the reliability under the same number of TSVs.
ISSN:2150-5942
DOI:10.1109/IMPACT.2016.7800033