A topology-based method for identifying flip-flop graphs in BJT circuits

This paper presents a method focused on finding embedded flip-flop graphs in circuit topology. The method is based on performing a tearing of the graph of the dead network. It is implemented in a methodological way by applying a series of graph operations. The method is applied to networks containin...

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Bibliographic Details
Main Authors: Vargas Bernal, R., Samtiento Reyes, A.
Format: Conference Proceeding
Language:English
Subjects:
Bipolar transistor circuits
Bonding
Circuit stability
Circuit topology
Coupling circuits
Ear
Flip-flops
Nonlinear optics
Resistors
Voltage
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Summary:This paper presents a method focused on finding embedded flip-flop graphs in circuit topology. The method is based on performing a tearing of the graph of the dead network. It is implemented in a methodological way by applying a series of graph operations. The method is applied to networks containing BJTs, independent current and voltage sources, and positive linear resistors but it can be easily modified to cope with other kinds of active devices.
DOI:10.1109/ISCAS.1999.780113