Fast Writeable Block-Aware Cache Update Policy for Spin-Transfer-Torque RAM

Spin-transfer-torque RAM (STT-RAM) is one of the emerging nonvolatile memories for last-level cache (LLC) featuring high density and low leakage. However, long latency for the write operation, which comes from the characteristics of nonvolatility, degrades performance when STT-RAM is employed as LLC...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2017-04, Vol.25 (4), p.1236-1249
Main Authors: Choi, Ju Hee, Kwak, Jong Wook
Format: Article
Language:English
Subjects:
Analytical models
Arrays
Asymmetric write architecture
Magnetic domain walls
Magnetic tunneling
Nonvolatile memory
nonvolatile memory (NVM)
Random access memory
spin-transfer-torque RAM (STT-RAM)
Switches
write latency
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Summary:Spin-transfer-torque RAM (STT-RAM) is one of the emerging nonvolatile memories for last-level cache (LLC) featuring high density and low leakage. However, long latency for the write operation, which comes from the characteristics of nonvolatility, degrades performance when STT-RAM is employed as LLC. To overcome this problem, we revisit the existing cache update policy and propose a new cache update policy to exploit the asymmetric write characteristics of STT-RAM. In our proposal, the data are written into a fast writeable block, regardless of the original position when the block arrives at the LLC. This paper proves the efficiency of our update policy based on analytical models and gives detailed information for implementing the policy. The experimental results show our scheme reduces slow writes by 77.6%, which leads a 31.1% reduction in write latency.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2016.2637897