High speed efficient FPGA implementation of pipelined AES S-Box

• Main Authors: Oukili, Soufiane, Bri, Seddik, Senthil Kumar, A. V.
• Format: Conference Proceeding
• Language: English
• Subjects: Advanced Encryption Standard; Algorithm design and analysis; combinational logic; Delays; Efficient; Encryption; Field programmable gate arrays; FPGA; Hardware; High speed; Pipeline processing; Registers; S-box substitution
• ISSN: 2327-1884
• DOI: 10.1109/CIST.2016.7805015

Smart City is becoming a commonly-used term to describe the concept of utilizing information and communication technologies (ICT) to enhance urban services and improve the quality of life for citizens. All communications should be fast and properly protected against unauthorized eavesdropping, interception, and modification. Therefore high speed and strong cryptography is required. Advanced Encryption Standard (AES) is the most widely and secure symmetric key encryption algorithms today. S-box substitution is the only non-linear step in this algorithm. It is one of the most complicated and costly part of the system. In this article, we present high speed efficient S-box AES architecture using combinational logic. We have used 5-stage pipeline design in order to increase the speed and the maximum operation frequency. Therefore registers are inserted in optimal placements. The implementation has been successfully done by virtex-6 (xc6vlx240t) FPGA device using Xilinx ISE 14.7. Our proposed design achieves a frequency of 842.744 MHz and occupied 20 slices, whereas the highest operation frequency reported in the literature is 696.37 MHz using 32 slices.