A digital technique for reducing clock jitter effects in time-interleaved A/D converter

Time-interleaved A/D converter is an effective approach to increase the data throughput. However, it suffers from clock jitter existing in the multi-phase clocks, which degrade the converter's Spurious-Free-Dynamic-Range (SFDR) as well as the Signal-to-Noise Ratio (SNR). In this paper, a digita...

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Bibliographic Details
Main Authors: Huawen Jin, Lee, E.K.F.
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Degradation
Error correction
Interpolation
Jitter
Linearity
Sampling methods
Signal generators
Signal to noise ratio
Throughput
Online Access:Request full text
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Summary:Time-interleaved A/D converter is an effective approach to increase the data throughput. However, it suffers from clock jitter existing in the multi-phase clocks, which degrade the converter's Spurious-Free-Dynamic-Range (SFDR) as well as the Signal-to-Noise Ratio (SNR). In this paper, a digital technique is proposed to reduce these non-ideal effects by obtaining a better estimation on the output data through the use of interpolation. Simulation results show that the proposed technique significantly improves the SFDR by 20/spl sim/50 dB.
DOI:10.1109/ISCAS.1999.780726