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A digital technique for reducing clock jitter effects in time-interleaved A/D converter
Time-interleaved A/D converter is an effective approach to increase the data throughput. However, it suffers from clock jitter existing in the multi-phase clocks, which degrade the converter's Spurious-Free-Dynamic-Range (SFDR) as well as the Signal-to-Noise Ratio (SNR). In this paper, a digita...
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container_end_page | 333 vol.2 |
container_issue | |
container_start_page | 330 |
container_title | |
container_volume | 2 |
creator | Huawen Jin Lee, E.K.F. |
description | Time-interleaved A/D converter is an effective approach to increase the data throughput. However, it suffers from clock jitter existing in the multi-phase clocks, which degrade the converter's Spurious-Free-Dynamic-Range (SFDR) as well as the Signal-to-Noise Ratio (SNR). In this paper, a digital technique is proposed to reduce these non-ideal effects by obtaining a better estimation on the output data through the use of interpolation. Simulation results show that the proposed technique significantly improves the SFDR by 20/spl sim/50 dB. |
doi_str_mv | 10.1109/ISCAS.1999.780726 |
format | conference_proceeding |
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However, it suffers from clock jitter existing in the multi-phase clocks, which degrade the converter's Spurious-Free-Dynamic-Range (SFDR) as well as the Signal-to-Noise Ratio (SNR). In this paper, a digital technique is proposed to reduce these non-ideal effects by obtaining a better estimation on the output data through the use of interpolation. Simulation results show that the proposed technique significantly improves the SFDR by 20/spl sim/50 dB.</description><identifier>ISBN: 0780354710</identifier><identifier>ISBN: 9780780354715</identifier><identifier>DOI: 10.1109/ISCAS.1999.780726</identifier><language>eng</language><publisher>IEEE</publisher><subject>Clocks ; Degradation ; Error correction ; Interpolation ; Jitter ; Linearity ; Sampling methods ; Signal generators ; Signal to noise ratio ; Throughput</subject><ispartof>1999 IEEE International Symposium on Circuits and Systems (ISCAS), 1999, Vol.2, p.330-333 vol.2</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/780726$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2051,4035,4036,27904,54899</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/780726$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Huawen Jin</creatorcontrib><creatorcontrib>Lee, E.K.F.</creatorcontrib><title>A digital technique for reducing clock jitter effects in time-interleaved A/D converter</title><title>1999 IEEE International Symposium on Circuits and Systems (ISCAS)</title><addtitle>ISCAS</addtitle><description>Time-interleaved A/D converter is an effective approach to increase the data throughput. However, it suffers from clock jitter existing in the multi-phase clocks, which degrade the converter's Spurious-Free-Dynamic-Range (SFDR) as well as the Signal-to-Noise Ratio (SNR). In this paper, a digital technique is proposed to reduce these non-ideal effects by obtaining a better estimation on the output data through the use of interpolation. Simulation results show that the proposed technique significantly improves the SFDR by 20/spl sim/50 dB.</description><subject>Clocks</subject><subject>Degradation</subject><subject>Error correction</subject><subject>Interpolation</subject><subject>Jitter</subject><subject>Linearity</subject><subject>Sampling methods</subject><subject>Signal generators</subject><subject>Signal to noise ratio</subject><subject>Throughput</subject><isbn>0780354710</isbn><isbn>9780780354715</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1999</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNp9js0KgkAUhQci6M8HqNV9AW0mNZulWFFrg5Yi49Wu2VjjFPT2CbXubL7DdzaHsbngnhBcLo9pEqeekFJ60YZHq_WATXjf_DCIBB8xp-tq3icIuRTrMTvHUFBFNm_AorpoejwRytaAweKpSFegmlZdoSZr0QCWJSrbAWmwdEOXdG8bzF9YQLzcgmr1C03vZmxY5k2Hzo9TttjvTsnBJUTM7oZuuXln34v-3_EDSBxAzg</recordid><startdate>1999</startdate><enddate>1999</enddate><creator>Huawen Jin</creator><creator>Lee, E.K.F.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>1999</creationdate><title>A digital technique for reducing clock jitter effects in time-interleaved A/D converter</title><author>Huawen Jin ; Lee, E.K.F.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_7807263</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1999</creationdate><topic>Clocks</topic><topic>Degradation</topic><topic>Error correction</topic><topic>Interpolation</topic><topic>Jitter</topic><topic>Linearity</topic><topic>Sampling methods</topic><topic>Signal generators</topic><topic>Signal to noise ratio</topic><topic>Throughput</topic><toplevel>online_resources</toplevel><creatorcontrib>Huawen Jin</creatorcontrib><creatorcontrib>Lee, E.K.F.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Huawen Jin</au><au>Lee, E.K.F.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A digital technique for reducing clock jitter effects in time-interleaved A/D converter</atitle><btitle>1999 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>1999</date><risdate>1999</risdate><volume>2</volume><spage>330</spage><epage>333 vol.2</epage><pages>330-333 vol.2</pages><isbn>0780354710</isbn><isbn>9780780354715</isbn><abstract>Time-interleaved A/D converter is an effective approach to increase the data throughput. However, it suffers from clock jitter existing in the multi-phase clocks, which degrade the converter's Spurious-Free-Dynamic-Range (SFDR) as well as the Signal-to-Noise Ratio (SNR). In this paper, a digital technique is proposed to reduce these non-ideal effects by obtaining a better estimation on the output data through the use of interpolation. Simulation results show that the proposed technique significantly improves the SFDR by 20/spl sim/50 dB.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.1999.780726</doi></addata></record> |
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ispartof | 1999 IEEE International Symposium on Circuits and Systems (ISCAS), 1999, Vol.2, p.330-333 vol.2 |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Clocks Degradation Error correction Interpolation Jitter Linearity Sampling methods Signal generators Signal to noise ratio Throughput |
title | A digital technique for reducing clock jitter effects in time-interleaved A/D converter |
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