Parallel mixed-level power simulation based on spatiotemporal circuit partitioning

In this work we propose a technique for spatial and temporal partitioning of a logic circuit based on the nodes activity computed by using a simulation at an higher level of abstraction. Only those components that are activated by a given input vector are added to the detailed simulation netlist. Th...

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Bibliographic Details
Main Authors: Chinosi, M., Zafalon, R., Guardiani, C.
Format: Conference Proceeding
Language:English
Subjects:
Central Processing Unit
Circuit simulation
Computational modeling
Integrated circuit reliability
Logic circuits
Moore's Law
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Research and development
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Timing
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Summary:In this work we propose a technique for spatial and temporal partitioning of a logic circuit based on the nodes activity computed by using a simulation at an higher level of abstraction. Only those components that are activated by a given input vector are added to the detailed simulation netlist. The methodology is suitable for parallel implementation on a multi-processor environment and allows us to arbitrarily switch between fast and detailed levels of abstraction during the simulation run. The experimental results obtained on a significant set of benchmarks show that it is possible to obtain a considerable reduction in both CPU time and memory occupation together with a considerable degree of accuracy. Furthermore, the proposed technique easily fits in the existing industrial design flows.
DOI:10.1109/DAC.1999.781378