A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator

This paper presents a 2.5D integrated microprocessor die, memory die, and accelerator die with 2.5D silicon interposer I/Os. The use of such 2.5D silicon interposer I/Os provide a scalable interconnection for core-core (up to 32 cores), core-memory (4× storage capacity) and core-accelerator (4.4× sp...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2017-06, Vol.64 (6), p.1432-1443
Main Authors: P.D., Sai Manoj, Yu, Zhiyi, Yu, Hao, Lin, Jie, Zhu, Shikai, Yin, Yingying, Liu, Xu, Huang, Xiwei, Song, Chongshen, Zhang, Wenqi, Yan, Mei
Format: Article
Language:English
Subjects:
25D stacking
Analytics
Bandwidths
Channels
Computing time
Encryption
Energy efficiency
Energy management
high bandwidth
Mathematical analysis
Microprocessors
multicore microprocessor
Multicore processing
Pipelines
Power efficiency
Power management
Routing
SerDes
Silicon
silicon interposer
Storage capacity
Three-dimensional displays
Video data
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Summary:This paper presents a 2.5D integrated microprocessor die, memory die, and accelerator die with 2.5D silicon interposer I/Os. The use of such 2.5D silicon interposer I/Os provide a scalable interconnection for core-core (up to 32 cores), core-memory (4× storage capacity) and core-accelerator (4.4× speedup in H.264 decoder). The 2.5D integrated chip was implemented in GF 65 nm process with multicore microprocessor operated at 500 MHz under 1.2 V supply with 1.08 W power dissipation. A pair of 8 Gbps 2.5D silicon interposer I/O is designed for each of 12 inter-die communication channels, achieving a bandwidth of 24 GBps with 7.5 pJ/bit energy efficiency. As a result, the specified applications such as H.264 video data analytics and AES encryption can achieve significant performance improvement of throughput and energy efficiency.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2016.2647322