Loading…
Scalable, high-quality, SAT-based multi-layer escape routing
Escape routing for Printed Circuit Boards (PCBs) is an important problem arising from modern packaging with large numbers of densely spaced pins, such as BGAs. Single-layer escape routing has been well-studied, but large, dense BGAs often require multiple PCB layers to be fully escaped. Unfortunatel...
Saved in:
Main Authors: | , , |
---|---|
Format: | Conference Proceeding |
Language: | English |
Subjects: | |
Online Access: | Get full text |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
cited_by | |
---|---|
cites | |
container_end_page | 8 |
container_issue | |
container_start_page | 1 |
container_title | |
container_volume | |
creator | Bayless, Sam Hoos, Holger H. Hu, Alan J. |
description | Escape routing for Printed Circuit Boards (PCBs) is an important problem arising from modern packaging with large numbers of densely spaced pins, such as BGAs. Single-layer escape routing has been well-studied, but large, dense BGAs often require multiple PCB layers to be fully escaped. Unfortunately, multi-layer escape routing is much more challenging than single-layer escape routing, and currently lacks scalable, high-quality, automatic solutions. As a result, multilayer escape routing for high-end BGAs typically requires extensive human intervention in practice. This paper introduces a novel approach to multi-layer escape routing. Our approach builds on recent advances in SAT (Boolean satisfiability) solving, in particular, the solver MonoSAT, which efficiently supports network-flow constraints within a general constraint-solving framework. We formulate multi-layer escape routing in this framework and demonstrate scalability to the largest BGAs presently in common use, with more than 2000 pins. Our approach supports 45and 90-degree routing, simultaneously places traces and vias, and supports all commonly used via technologies, including through-hole, blind, buried, and any-layer micro-vias. In addition, because our approach is based on constraint-solving, it can flexibly interoperate with partial solutions from other routing techniques. We demonstrate the utility of our technique by finding escape routings for a diverse set of large, commercial BGAs. Compared to a typical layer-by-layer approach, our approach produces better routings, often saving one or more PCB layers for larger BGAs, and in some cases, proving that no solution is possible with fewer layers. Finally, we describe how our technique can be extended to handle common additional constraints, such as differential-pair constraints. |
doi_str_mv | 10.1145/2966986.2967072 |
format | conference_proceeding |
fullrecord | <record><control><sourceid>ieee</sourceid><recordid>TN_cdi_ieee_primary_7827599</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>7827599</ieee_id><sourcerecordid>7827599</sourcerecordid><originalsourceid>FETCH-LOGICAL-a255t-3ef130b37ccd90a8d306089e68346e1e491d9a4e26039422d3d5a446b80932473</originalsourceid><addsrcrecordid>eNotjrtKA0EUQEdBMInWFjb7AZl4Z-48wSYEXxCwSKzD3d2bZGSicR_F_r0LWh04xeEIcadgoZSxDzo6F4NbjPTg9YWYjhbQGOfcpZgoa4PUBs21mLbtJ4AGHdxEPG4qylRmnhfHdDjKn55y6oZ5sVluZUkt18Wpz12SmQZuCm4rOnPRfPdd-jrciKs95ZZv_zkTH89P29WrXL-_vK2Wa0na2k4i7xVCib6q6ggUagQHIbILaBwrNlHVkQxrBxiN1jXWlsbxMkBEbTzOxP1fNzHz7tykEzXDzgftbYz4C4MVRPA</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Scalable, high-quality, SAT-based multi-layer escape routing</title><source>IEEE Xplore All Conference Series</source><creator>Bayless, Sam ; Hoos, Holger H. ; Hu, Alan J.</creator><creatorcontrib>Bayless, Sam ; Hoos, Holger H. ; Hu, Alan J.</creatorcontrib><description>Escape routing for Printed Circuit Boards (PCBs) is an important problem arising from modern packaging with large numbers of densely spaced pins, such as BGAs. Single-layer escape routing has been well-studied, but large, dense BGAs often require multiple PCB layers to be fully escaped. Unfortunately, multi-layer escape routing is much more challenging than single-layer escape routing, and currently lacks scalable, high-quality, automatic solutions. As a result, multilayer escape routing for high-end BGAs typically requires extensive human intervention in practice. This paper introduces a novel approach to multi-layer escape routing. Our approach builds on recent advances in SAT (Boolean satisfiability) solving, in particular, the solver MonoSAT, which efficiently supports network-flow constraints within a general constraint-solving framework. We formulate multi-layer escape routing in this framework and demonstrate scalability to the largest BGAs presently in common use, with more than 2000 pins. Our approach supports 45and 90-degree routing, simultaneously places traces and vias, and supports all commonly used via technologies, including through-hole, blind, buried, and any-layer micro-vias. In addition, because our approach is based on constraint-solving, it can flexibly interoperate with partial solutions from other routing techniques. We demonstrate the utility of our technique by finding escape routings for a diverse set of large, commercial BGAs. Compared to a typical layer-by-layer approach, our approach produces better routings, often saving one or more PCB layers for larger BGAs, and in some cases, proving that no solution is possible with fewer layers. Finally, we describe how our technique can be extended to handle common additional constraints, such as differential-pair constraints.</description><identifier>EISSN: 1558-2434</identifier><identifier>EISBN: 1450344666</identifier><identifier>EISBN: 9781450344661</identifier><identifier>DOI: 10.1145/2966986.2967072</identifier><language>eng</language><publisher>ACM</publisher><subject>Electronics packaging ; Encoding ; Pins ; Printed circuits ; Routing ; Scalability ; Wires</subject><ispartof>2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2016, p.1-8</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7827599$$EHTML$$P50$$Gieee$$Hfree_for_read</linktohtml><link.rule.ids>309,310,777,781,786,787,23911,23912,25121,27906,54536,54913</link.rule.ids></links><search><creatorcontrib>Bayless, Sam</creatorcontrib><creatorcontrib>Hoos, Holger H.</creatorcontrib><creatorcontrib>Hu, Alan J.</creatorcontrib><title>Scalable, high-quality, SAT-based multi-layer escape routing</title><title>2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)</title><addtitle>ICCAD</addtitle><description>Escape routing for Printed Circuit Boards (PCBs) is an important problem arising from modern packaging with large numbers of densely spaced pins, such as BGAs. Single-layer escape routing has been well-studied, but large, dense BGAs often require multiple PCB layers to be fully escaped. Unfortunately, multi-layer escape routing is much more challenging than single-layer escape routing, and currently lacks scalable, high-quality, automatic solutions. As a result, multilayer escape routing for high-end BGAs typically requires extensive human intervention in practice. This paper introduces a novel approach to multi-layer escape routing. Our approach builds on recent advances in SAT (Boolean satisfiability) solving, in particular, the solver MonoSAT, which efficiently supports network-flow constraints within a general constraint-solving framework. We formulate multi-layer escape routing in this framework and demonstrate scalability to the largest BGAs presently in common use, with more than 2000 pins. Our approach supports 45and 90-degree routing, simultaneously places traces and vias, and supports all commonly used via technologies, including through-hole, blind, buried, and any-layer micro-vias. In addition, because our approach is based on constraint-solving, it can flexibly interoperate with partial solutions from other routing techniques. We demonstrate the utility of our technique by finding escape routings for a diverse set of large, commercial BGAs. Compared to a typical layer-by-layer approach, our approach produces better routings, often saving one or more PCB layers for larger BGAs, and in some cases, proving that no solution is possible with fewer layers. Finally, we describe how our technique can be extended to handle common additional constraints, such as differential-pair constraints.</description><subject>Electronics packaging</subject><subject>Encoding</subject><subject>Pins</subject><subject>Printed circuits</subject><subject>Routing</subject><subject>Scalability</subject><subject>Wires</subject><issn>1558-2434</issn><isbn>1450344666</isbn><isbn>9781450344661</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2016</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>ESBDL</sourceid><recordid>eNotjrtKA0EUQEdBMInWFjb7AZl4Z-48wSYEXxCwSKzD3d2bZGSicR_F_r0LWh04xeEIcadgoZSxDzo6F4NbjPTg9YWYjhbQGOfcpZgoa4PUBs21mLbtJ4AGHdxEPG4qylRmnhfHdDjKn55y6oZ5sVluZUkt18Wpz12SmQZuCm4rOnPRfPdd-jrciKs95ZZv_zkTH89P29WrXL-_vK2Wa0na2k4i7xVCib6q6ggUagQHIbILaBwrNlHVkQxrBxiN1jXWlsbxMkBEbTzOxP1fNzHz7tykEzXDzgftbYz4C4MVRPA</recordid><startdate>20161107</startdate><enddate>20161107</enddate><creator>Bayless, Sam</creator><creator>Hoos, Holger H.</creator><creator>Hu, Alan J.</creator><general>ACM</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>ESBDL</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>20161107</creationdate><title>Scalable, high-quality, SAT-based multi-layer escape routing</title><author>Bayless, Sam ; Hoos, Holger H. ; Hu, Alan J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-a255t-3ef130b37ccd90a8d306089e68346e1e491d9a4e26039422d3d5a446b80932473</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2016</creationdate><topic>Electronics packaging</topic><topic>Encoding</topic><topic>Pins</topic><topic>Printed circuits</topic><topic>Routing</topic><topic>Scalability</topic><topic>Wires</topic><toplevel>online_resources</toplevel><creatorcontrib>Bayless, Sam</creatorcontrib><creatorcontrib>Hoos, Holger H.</creatorcontrib><creatorcontrib>Hu, Alan J.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore Open Access Journals</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Bayless, Sam</au><au>Hoos, Holger H.</au><au>Hu, Alan J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Scalable, high-quality, SAT-based multi-layer escape routing</atitle><btitle>2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)</btitle><stitle>ICCAD</stitle><date>2016-11-07</date><risdate>2016</risdate><spage>1</spage><epage>8</epage><pages>1-8</pages><eissn>1558-2434</eissn><eisbn>1450344666</eisbn><eisbn>9781450344661</eisbn><abstract>Escape routing for Printed Circuit Boards (PCBs) is an important problem arising from modern packaging with large numbers of densely spaced pins, such as BGAs. Single-layer escape routing has been well-studied, but large, dense BGAs often require multiple PCB layers to be fully escaped. Unfortunately, multi-layer escape routing is much more challenging than single-layer escape routing, and currently lacks scalable, high-quality, automatic solutions. As a result, multilayer escape routing for high-end BGAs typically requires extensive human intervention in practice. This paper introduces a novel approach to multi-layer escape routing. Our approach builds on recent advances in SAT (Boolean satisfiability) solving, in particular, the solver MonoSAT, which efficiently supports network-flow constraints within a general constraint-solving framework. We formulate multi-layer escape routing in this framework and demonstrate scalability to the largest BGAs presently in common use, with more than 2000 pins. Our approach supports 45and 90-degree routing, simultaneously places traces and vias, and supports all commonly used via technologies, including through-hole, blind, buried, and any-layer micro-vias. In addition, because our approach is based on constraint-solving, it can flexibly interoperate with partial solutions from other routing techniques. We demonstrate the utility of our technique by finding escape routings for a diverse set of large, commercial BGAs. Compared to a typical layer-by-layer approach, our approach produces better routings, often saving one or more PCB layers for larger BGAs, and in some cases, proving that no solution is possible with fewer layers. Finally, we describe how our technique can be extended to handle common additional constraints, such as differential-pair constraints.</abstract><pub>ACM</pub><doi>10.1145/2966986.2967072</doi><tpages>8</tpages><oa>free_for_read</oa></addata></record> |
fulltext | fulltext |
identifier | EISSN: 1558-2434 |
ispartof | 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2016, p.1-8 |
issn | 1558-2434 |
language | eng |
recordid | cdi_ieee_primary_7827599 |
source | IEEE Xplore All Conference Series |
subjects | Electronics packaging Encoding Pins Printed circuits Routing Scalability Wires |
title | Scalable, high-quality, SAT-based multi-layer escape routing |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-17T22%3A54%3A48IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Scalable,%20high-quality,%20SAT-based%20multi-layer%20escape%20routing&rft.btitle=2016%20IEEE/ACM%20International%20Conference%20on%20Computer-Aided%20Design%20(ICCAD)&rft.au=Bayless,%20Sam&rft.date=2016-11-07&rft.spage=1&rft.epage=8&rft.pages=1-8&rft.eissn=1558-2434&rft_id=info:doi/10.1145/2966986.2967072&rft.eisbn=1450344666&rft.eisbn_list=9781450344661&rft_dat=%3Cieee%3E7827599%3C/ieee%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-a255t-3ef130b37ccd90a8d306089e68346e1e491d9a4e26039422d3d5a446b80932473%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=7827599&rfr_iscdi=true |