Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT

Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The perfo...

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Main Authors: Tsutsui, Gen, Ruqiang Bao, Kwan-yong Lim, Robison, Robert R., Vega, Reinaldo A., Jie Yang, Zuoguang Liu, Miaomiao Wang, Gluschenkov, Oleg, Chun Wing Yeung, Watanabe, Koji, Bentley, Steven, Niimi, Hiroaki, Liu, Derrick, Huimei Zhou, Siddiqui, Shariq, Hoon Kim, Galatage, Rohit, Venigalla, Rajasekhar, Raymond, Mark, Adusumilli, Praneet, Mochizuki, Shogo, Devarajan, Thamarai S., Miao, Bruce, Bei Liu, Greene, Andrew, Shearer, Jeffrey, Montanini, Pietro, Strane, Jay W., Prindle, Christopher, Miller, Eric R., Fronheiser, Jody, Niu, Chengyu C., Kisup Chung, Kelly, James J., Jagannathan, Hemanth, Kanakasabapathy, Sivananda, Karve, Gauri, Fee Li Lie, Oldiges, Philip, Narayanan, Vijay, Hook, Terence B., Knorr, Andreas, Gupta, Dinesh, Guo, Dechao, Divakaruni, Rama, Huiming Bu, Khare, Mukesh
Format: Conference Proceeding
Language:English
Subjects:
Doping
FinFETs
Junctions
Optimization
Resistance
Silicides
Silicon germanium
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Summary:Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.
ISSN:2156-017X
DOI:10.1109/IEDM.2016.7838439