Loading…
Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT
Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The perfo...
Saved in:
| Main Authors: | , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , |
|---|---|
| Format: | Conference Proceeding |
| Language: | English |
| Subjects: | |
| Online Access: | Request full text |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| cited_by | |
|---|---|
| cites | |
| container_end_page | 17.4.4 |
| container_issue | |
| container_start_page | 17.4.1 |
| container_title | |
| container_volume | |
| creator | Tsutsui, Gen Ruqiang Bao Kwan-yong Lim Robison, Robert R. Vega, Reinaldo A. Jie Yang Zuoguang Liu Miaomiao Wang Gluschenkov, Oleg Chun Wing Yeung Watanabe, Koji Bentley, Steven Niimi, Hiroaki Liu, Derrick Huimei Zhou Siddiqui, Shariq Hoon Kim Galatage, Rohit Venigalla, Rajasekhar Raymond, Mark Adusumilli, Praneet Mochizuki, Shogo Devarajan, Thamarai S. Miao, Bruce Bei Liu Greene, Andrew Shearer, Jeffrey Montanini, Pietro Strane, Jay W. Prindle, Christopher Miller, Eric R. Fronheiser, Jody Niu, Chengyu C. Kisup Chung Kelly, James J. Jagannathan, Hemanth Kanakasabapathy, Sivananda Karve, Gauri Fee Li Lie Oldiges, Philip Narayanan, Vijay Hook, Terence B. Knorr, Andreas Gupta, Dinesh Guo, Dechao Divakaruni, Rama Huiming Bu Khare, Mukesh |
| description | Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes. |
| doi_str_mv | 10.1109/IEDM.2016.7838439 |
| format | conference_proceeding |
| fullrecord | <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_7838439</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>7838439</ieee_id><sourcerecordid>7838439</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-b3aad577f8adcf96cd5792dae4a5e024007753b6498bde0de99284d79c3d3a6e3</originalsourceid><addsrcrecordid>eNotj7FqwzAURdVCoWmaDyhd9AN2niTL0huLE6eGhAz20C3I1nOjYjvBDoX8fQPNdDlnOHAZexMQCwG4LNarXSxBpLGxyiYKH9gCjRUaEBSCxEc2k0KnEQjz9cxepukHQBqNesaKiprjcOpO31f-G1zdEV9l_Exjexp7NzTEqaOehsvEb4aXYVmGDfHm6IaBOp7t9iXPw5BX1St7al030eK-c1bl6yr7jLb7TZF9bKOAcIlq5ZzXxrTW-abFtLkBSu8ocZpAJgDGaFWnCdraE3hClDbxBhvllUtJzdn7fzYQ0eE8ht6N18P9uPoDMeRL8w</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT</title><source>IEEE Xplore All Conference Series</source><creator>Tsutsui, Gen ; Ruqiang Bao ; Kwan-yong Lim ; Robison, Robert R. ; Vega, Reinaldo A. ; Jie Yang ; Zuoguang Liu ; Miaomiao Wang ; Gluschenkov, Oleg ; Chun Wing Yeung ; Watanabe, Koji ; Bentley, Steven ; Niimi, Hiroaki ; Liu, Derrick ; Huimei Zhou ; Siddiqui, Shariq ; Hoon Kim ; Galatage, Rohit ; Venigalla, Rajasekhar ; Raymond, Mark ; Adusumilli, Praneet ; Mochizuki, Shogo ; Devarajan, Thamarai S. ; Miao, Bruce ; Bei Liu ; Greene, Andrew ; Shearer, Jeffrey ; Montanini, Pietro ; Strane, Jay W. ; Prindle, Christopher ; Miller, Eric R. ; Fronheiser, Jody ; Niu, Chengyu C. ; Kisup Chung ; Kelly, James J. ; Jagannathan, Hemanth ; Kanakasabapathy, Sivananda ; Karve, Gauri ; Fee Li Lie ; Oldiges, Philip ; Narayanan, Vijay ; Hook, Terence B. ; Knorr, Andreas ; Gupta, Dinesh ; Guo, Dechao ; Divakaruni, Rama ; Huiming Bu ; Khare, Mukesh</creator><creatorcontrib>Tsutsui, Gen ; Ruqiang Bao ; Kwan-yong Lim ; Robison, Robert R. ; Vega, Reinaldo A. ; Jie Yang ; Zuoguang Liu ; Miaomiao Wang ; Gluschenkov, Oleg ; Chun Wing Yeung ; Watanabe, Koji ; Bentley, Steven ; Niimi, Hiroaki ; Liu, Derrick ; Huimei Zhou ; Siddiqui, Shariq ; Hoon Kim ; Galatage, Rohit ; Venigalla, Rajasekhar ; Raymond, Mark ; Adusumilli, Praneet ; Mochizuki, Shogo ; Devarajan, Thamarai S. ; Miao, Bruce ; Bei Liu ; Greene, Andrew ; Shearer, Jeffrey ; Montanini, Pietro ; Strane, Jay W. ; Prindle, Christopher ; Miller, Eric R. ; Fronheiser, Jody ; Niu, Chengyu C. ; Kisup Chung ; Kelly, James J. ; Jagannathan, Hemanth ; Kanakasabapathy, Sivananda ; Karve, Gauri ; Fee Li Lie ; Oldiges, Philip ; Narayanan, Vijay ; Hook, Terence B. ; Knorr, Andreas ; Gupta, Dinesh ; Guo, Dechao ; Divakaruni, Rama ; Huiming Bu ; Khare, Mukesh</creatorcontrib><description>Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.</description><identifier>EISSN: 2156-017X</identifier><identifier>EISBN: 9781509039029</identifier><identifier>EISBN: 1509039023</identifier><identifier>DOI: 10.1109/IEDM.2016.7838439</identifier><language>eng</language><publisher>IEEE</publisher><subject>Doping ; FinFETs ; Junctions ; Optimization ; Resistance ; Silicides ; Silicon germanium</subject><ispartof>2016 IEEE International Electron Devices Meeting (IEDM), 2016, p.17.4.1-17.4.4</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7838439$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,27925,54555,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/7838439$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Tsutsui, Gen</creatorcontrib><creatorcontrib>Ruqiang Bao</creatorcontrib><creatorcontrib>Kwan-yong Lim</creatorcontrib><creatorcontrib>Robison, Robert R.</creatorcontrib><creatorcontrib>Vega, Reinaldo A.</creatorcontrib><creatorcontrib>Jie Yang</creatorcontrib><creatorcontrib>Zuoguang Liu</creatorcontrib><creatorcontrib>Miaomiao Wang</creatorcontrib><creatorcontrib>Gluschenkov, Oleg</creatorcontrib><creatorcontrib>Chun Wing Yeung</creatorcontrib><creatorcontrib>Watanabe, Koji</creatorcontrib><creatorcontrib>Bentley, Steven</creatorcontrib><creatorcontrib>Niimi, Hiroaki</creatorcontrib><creatorcontrib>Liu, Derrick</creatorcontrib><creatorcontrib>Huimei Zhou</creatorcontrib><creatorcontrib>Siddiqui, Shariq</creatorcontrib><creatorcontrib>Hoon Kim</creatorcontrib><creatorcontrib>Galatage, Rohit</creatorcontrib><creatorcontrib>Venigalla, Rajasekhar</creatorcontrib><creatorcontrib>Raymond, Mark</creatorcontrib><creatorcontrib>Adusumilli, Praneet</creatorcontrib><creatorcontrib>Mochizuki, Shogo</creatorcontrib><creatorcontrib>Devarajan, Thamarai S.</creatorcontrib><creatorcontrib>Miao, Bruce</creatorcontrib><creatorcontrib>Bei Liu</creatorcontrib><creatorcontrib>Greene, Andrew</creatorcontrib><creatorcontrib>Shearer, Jeffrey</creatorcontrib><creatorcontrib>Montanini, Pietro</creatorcontrib><creatorcontrib>Strane, Jay W.</creatorcontrib><creatorcontrib>Prindle, Christopher</creatorcontrib><creatorcontrib>Miller, Eric R.</creatorcontrib><creatorcontrib>Fronheiser, Jody</creatorcontrib><creatorcontrib>Niu, Chengyu C.</creatorcontrib><creatorcontrib>Kisup Chung</creatorcontrib><creatorcontrib>Kelly, James J.</creatorcontrib><creatorcontrib>Jagannathan, Hemanth</creatorcontrib><creatorcontrib>Kanakasabapathy, Sivananda</creatorcontrib><creatorcontrib>Karve, Gauri</creatorcontrib><creatorcontrib>Fee Li Lie</creatorcontrib><creatorcontrib>Oldiges, Philip</creatorcontrib><creatorcontrib>Narayanan, Vijay</creatorcontrib><creatorcontrib>Hook, Terence B.</creatorcontrib><creatorcontrib>Knorr, Andreas</creatorcontrib><creatorcontrib>Gupta, Dinesh</creatorcontrib><creatorcontrib>Guo, Dechao</creatorcontrib><creatorcontrib>Divakaruni, Rama</creatorcontrib><creatorcontrib>Huiming Bu</creatorcontrib><creatorcontrib>Khare, Mukesh</creatorcontrib><title>Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT</title><title>2016 IEEE International Electron Devices Meeting (IEDM)</title><addtitle>IEDM</addtitle><description>Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.</description><subject>Doping</subject><subject>FinFETs</subject><subject>Junctions</subject><subject>Optimization</subject><subject>Resistance</subject><subject>Silicides</subject><subject>Silicon germanium</subject><issn>2156-017X</issn><isbn>9781509039029</isbn><isbn>1509039023</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2016</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotj7FqwzAURdVCoWmaDyhd9AN2niTL0huLE6eGhAz20C3I1nOjYjvBDoX8fQPNdDlnOHAZexMQCwG4LNarXSxBpLGxyiYKH9gCjRUaEBSCxEc2k0KnEQjz9cxepukHQBqNesaKiprjcOpO31f-G1zdEV9l_Exjexp7NzTEqaOehsvEb4aXYVmGDfHm6IaBOp7t9iXPw5BX1St7al030eK-c1bl6yr7jLb7TZF9bKOAcIlq5ZzXxrTW-abFtLkBSu8ocZpAJgDGaFWnCdraE3hClDbxBhvllUtJzdn7fzYQ0eE8ht6N18P9uPoDMeRL8w</recordid><startdate>201612</startdate><enddate>201612</enddate><creator>Tsutsui, Gen</creator><creator>Ruqiang Bao</creator><creator>Kwan-yong Lim</creator><creator>Robison, Robert R.</creator><creator>Vega, Reinaldo A.</creator><creator>Jie Yang</creator><creator>Zuoguang Liu</creator><creator>Miaomiao Wang</creator><creator>Gluschenkov, Oleg</creator><creator>Chun Wing Yeung</creator><creator>Watanabe, Koji</creator><creator>Bentley, Steven</creator><creator>Niimi, Hiroaki</creator><creator>Liu, Derrick</creator><creator>Huimei Zhou</creator><creator>Siddiqui, Shariq</creator><creator>Hoon Kim</creator><creator>Galatage, Rohit</creator><creator>Venigalla, Rajasekhar</creator><creator>Raymond, Mark</creator><creator>Adusumilli, Praneet</creator><creator>Mochizuki, Shogo</creator><creator>Devarajan, Thamarai S.</creator><creator>Miao, Bruce</creator><creator>Bei Liu</creator><creator>Greene, Andrew</creator><creator>Shearer, Jeffrey</creator><creator>Montanini, Pietro</creator><creator>Strane, Jay W.</creator><creator>Prindle, Christopher</creator><creator>Miller, Eric R.</creator><creator>Fronheiser, Jody</creator><creator>Niu, Chengyu C.</creator><creator>Kisup Chung</creator><creator>Kelly, James J.</creator><creator>Jagannathan, Hemanth</creator><creator>Kanakasabapathy, Sivananda</creator><creator>Karve, Gauri</creator><creator>Fee Li Lie</creator><creator>Oldiges, Philip</creator><creator>Narayanan, Vijay</creator><creator>Hook, Terence B.</creator><creator>Knorr, Andreas</creator><creator>Gupta, Dinesh</creator><creator>Guo, Dechao</creator><creator>Divakaruni, Rama</creator><creator>Huiming Bu</creator><creator>Khare, Mukesh</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201612</creationdate><title>Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT</title><author>Tsutsui, Gen ; Ruqiang Bao ; Kwan-yong Lim ; Robison, Robert R. ; Vega, Reinaldo A. ; Jie Yang ; Zuoguang Liu ; Miaomiao Wang ; Gluschenkov, Oleg ; Chun Wing Yeung ; Watanabe, Koji ; Bentley, Steven ; Niimi, Hiroaki ; Liu, Derrick ; Huimei Zhou ; Siddiqui, Shariq ; Hoon Kim ; Galatage, Rohit ; Venigalla, Rajasekhar ; Raymond, Mark ; Adusumilli, Praneet ; Mochizuki, Shogo ; Devarajan, Thamarai S. ; Miao, Bruce ; Bei Liu ; Greene, Andrew ; Shearer, Jeffrey ; Montanini, Pietro ; Strane, Jay W. ; Prindle, Christopher ; Miller, Eric R. ; Fronheiser, Jody ; Niu, Chengyu C. ; Kisup Chung ; Kelly, James J. ; Jagannathan, Hemanth ; Kanakasabapathy, Sivananda ; Karve, Gauri ; Fee Li Lie ; Oldiges, Philip ; Narayanan, Vijay ; Hook, Terence B. ; Knorr, Andreas ; Gupta, Dinesh ; Guo, Dechao ; Divakaruni, Rama ; Huiming Bu ; Khare, Mukesh</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-b3aad577f8adcf96cd5792dae4a5e024007753b6498bde0de99284d79c3d3a6e3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2016</creationdate><topic>Doping</topic><topic>FinFETs</topic><topic>Junctions</topic><topic>Optimization</topic><topic>Resistance</topic><topic>Silicides</topic><topic>Silicon germanium</topic><toplevel>online_resources</toplevel><creatorcontrib>Tsutsui, Gen</creatorcontrib><creatorcontrib>Ruqiang Bao</creatorcontrib><creatorcontrib>Kwan-yong Lim</creatorcontrib><creatorcontrib>Robison, Robert R.</creatorcontrib><creatorcontrib>Vega, Reinaldo A.</creatorcontrib><creatorcontrib>Jie Yang</creatorcontrib><creatorcontrib>Zuoguang Liu</creatorcontrib><creatorcontrib>Miaomiao Wang</creatorcontrib><creatorcontrib>Gluschenkov, Oleg</creatorcontrib><creatorcontrib>Chun Wing Yeung</creatorcontrib><creatorcontrib>Watanabe, Koji</creatorcontrib><creatorcontrib>Bentley, Steven</creatorcontrib><creatorcontrib>Niimi, Hiroaki</creatorcontrib><creatorcontrib>Liu, Derrick</creatorcontrib><creatorcontrib>Huimei Zhou</creatorcontrib><creatorcontrib>Siddiqui, Shariq</creatorcontrib><creatorcontrib>Hoon Kim</creatorcontrib><creatorcontrib>Galatage, Rohit</creatorcontrib><creatorcontrib>Venigalla, Rajasekhar</creatorcontrib><creatorcontrib>Raymond, Mark</creatorcontrib><creatorcontrib>Adusumilli, Praneet</creatorcontrib><creatorcontrib>Mochizuki, Shogo</creatorcontrib><creatorcontrib>Devarajan, Thamarai S.</creatorcontrib><creatorcontrib>Miao, Bruce</creatorcontrib><creatorcontrib>Bei Liu</creatorcontrib><creatorcontrib>Greene, Andrew</creatorcontrib><creatorcontrib>Shearer, Jeffrey</creatorcontrib><creatorcontrib>Montanini, Pietro</creatorcontrib><creatorcontrib>Strane, Jay W.</creatorcontrib><creatorcontrib>Prindle, Christopher</creatorcontrib><creatorcontrib>Miller, Eric R.</creatorcontrib><creatorcontrib>Fronheiser, Jody</creatorcontrib><creatorcontrib>Niu, Chengyu C.</creatorcontrib><creatorcontrib>Kisup Chung</creatorcontrib><creatorcontrib>Kelly, James J.</creatorcontrib><creatorcontrib>Jagannathan, Hemanth</creatorcontrib><creatorcontrib>Kanakasabapathy, Sivananda</creatorcontrib><creatorcontrib>Karve, Gauri</creatorcontrib><creatorcontrib>Fee Li Lie</creatorcontrib><creatorcontrib>Oldiges, Philip</creatorcontrib><creatorcontrib>Narayanan, Vijay</creatorcontrib><creatorcontrib>Hook, Terence B.</creatorcontrib><creatorcontrib>Knorr, Andreas</creatorcontrib><creatorcontrib>Gupta, Dinesh</creatorcontrib><creatorcontrib>Guo, Dechao</creatorcontrib><creatorcontrib>Divakaruni, Rama</creatorcontrib><creatorcontrib>Huiming Bu</creatorcontrib><creatorcontrib>Khare, Mukesh</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tsutsui, Gen</au><au>Ruqiang Bao</au><au>Kwan-yong Lim</au><au>Robison, Robert R.</au><au>Vega, Reinaldo A.</au><au>Jie Yang</au><au>Zuoguang Liu</au><au>Miaomiao Wang</au><au>Gluschenkov, Oleg</au><au>Chun Wing Yeung</au><au>Watanabe, Koji</au><au>Bentley, Steven</au><au>Niimi, Hiroaki</au><au>Liu, Derrick</au><au>Huimei Zhou</au><au>Siddiqui, Shariq</au><au>Hoon Kim</au><au>Galatage, Rohit</au><au>Venigalla, Rajasekhar</au><au>Raymond, Mark</au><au>Adusumilli, Praneet</au><au>Mochizuki, Shogo</au><au>Devarajan, Thamarai S.</au><au>Miao, Bruce</au><au>Bei Liu</au><au>Greene, Andrew</au><au>Shearer, Jeffrey</au><au>Montanini, Pietro</au><au>Strane, Jay W.</au><au>Prindle, Christopher</au><au>Miller, Eric R.</au><au>Fronheiser, Jody</au><au>Niu, Chengyu C.</au><au>Kisup Chung</au><au>Kelly, James J.</au><au>Jagannathan, Hemanth</au><au>Kanakasabapathy, Sivananda</au><au>Karve, Gauri</au><au>Fee Li Lie</au><au>Oldiges, Philip</au><au>Narayanan, Vijay</au><au>Hook, Terence B.</au><au>Knorr, Andreas</au><au>Gupta, Dinesh</au><au>Guo, Dechao</au><au>Divakaruni, Rama</au><au>Huiming Bu</au><au>Khare, Mukesh</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT</atitle><btitle>2016 IEEE International Electron Devices Meeting (IEDM)</btitle><stitle>IEDM</stitle><date>2016-12</date><risdate>2016</risdate><spage>17.4.1</spage><epage>17.4.4</epage><pages>17.4.1-17.4.4</pages><eissn>2156-017X</eissn><eisbn>9781509039029</eisbn><eisbn>1509039023</eisbn><abstract>Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.</abstract><pub>IEEE</pub><doi>10.1109/IEDM.2016.7838439</doi></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | EISSN: 2156-017X |
| ispartof | 2016 IEEE International Electron Devices Meeting (IEDM), 2016, p.17.4.1-17.4.4 |
| issn | 2156-017X |
| language | eng |
| recordid | cdi_ieee_primary_7838439 |
| source | IEEE Xplore All Conference Series |
| subjects | Doping FinFETs Junctions Optimization Resistance Silicides Silicon germanium |
| title | Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT |
| url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-25T15%3A04%3A59IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Technology%20viable%20DC%20performance%20elements%20for%20Si/SiGe%20channel%20CMOS%20FinFTT&rft.btitle=2016%20IEEE%20International%20Electron%20Devices%20Meeting%20(IEDM)&rft.au=Tsutsui,%20Gen&rft.date=2016-12&rft.spage=17.4.1&rft.epage=17.4.4&rft.pages=17.4.1-17.4.4&rft.eissn=2156-017X&rft_id=info:doi/10.1109/IEDM.2016.7838439&rft.eisbn=9781509039029&rft.eisbn_list=1509039023&rft_dat=%3Cieee_CHZPO%3E7838439%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i90t-b3aad577f8adcf96cd5792dae4a5e024007753b6498bde0de99284d79c3d3a6e3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=7838439&rfr_iscdi=true |