Embedded FPGA accelerator for Wireless Sensor Network nodes

with the increasing complexity of system on chip designs, the possibility of introducing changes after production becomes interesting. Therefore the integration of an embedded FPGA (eFPGA) in a System on Chip (SoC) allows the reuse of a portion of the chip. In the WSN nodes, dimensions of the chip s...

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Bibliographic Details
Main Authors: Saidi, Hajer, Turki, Mariem, Marrakchi, Zied, Ben Saleh, Mohammed S., Abid, Mohamed
Format: Conference Proceeding
Language:English
Subjects:
ARM
Computer architecture
Coprocessors
eFPGA
Field programmable gate arrays
Hardware
reconfigurable
SoC
Software
Switches
Wireless sensor networks
WSN
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Description
Summary:with the increasing complexity of system on chip designs, the possibility of introducing changes after production becomes interesting. Therefore the integration of an embedded FPGA (eFPGA) in a System on Chip (SoC) allows the reuse of a portion of the chip. In the WSN nodes, dimensions of the chip should be as small as possible to optimize several constraints such as power consumption, run time and the price. In this paper we propose to introduce a reconfigurable coprocessor which is able to be reconfigurable at a specific time with a specific algorithm instead of using a standalone coprocessor for each one. Indeed, we present software / hardware interface to include a reconfigurable part in a Cortex-M0-based SoC. The software part describes the way to configure and to use the e-FPGA. The hardware interface allows handling the communication between the e-FPGA and the AHB bus.
ISSN:2162-061X
DOI:10.1109/IDT.2016.7843061