A Scheme to Reduce the Number of Parity Check Bits in Orthogonal Latin Square Codes

The use of error-correcting codes is a common strategy to protect memories from errors. Single-error correction, double-error detection linear block codes have been traditionally utilized. However, there are applications where multiple errors are frequent and more complex codes are needed. Orthogona...

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Bibliographic Details
Published in:IEEE transactions on reliability 2017-06, Vol.66 (2), p.518-528
Main Authors: Reviriego, Pedro, Shanshan Liu, Sanchez-Macian, Alfonso, Liyi Xiao, Maestro, Juan Antonio
Format: Article
Language:English
Subjects:
Block codes
Circuits
Complexity
Complexity theory
Decoding
Delay
Delays
Double-error correction (DEC)
Error correction
Error correction & detection
Error correction codes
Error detection
error-correcting codes
Latin square design
Latin squares
Logic gates
Mathematical model
memory
Parity
Parity check codes
triple-error correction
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Summary:The use of error-correcting codes is a common strategy to protect memories from errors. Single-error correction, double-error detection linear block codes have been traditionally utilized. However, there are applications where multiple errors are frequent and more complex codes are needed. Orthogonal Latin square codes are one type of codes with multiple-error-correction capability. They are of interest for memory protection because they can be decoded with low complexity and delay. This paper presents a modification to orthogonal Latin square codes that reduces the number of parity check bits to be stored in memory therefore lowering the memory overhead needed to implement the codes. The proposed codes can also be decoded with low delay and complexity. This paper also presents an evaluation of the encoder and decoder implementations for various word sizes and compares them with the standard orthogonal Latin square implementations. The results show that they are similar in terms of circuit area and introduce only a small penalty in delay.
ISSN:0018-9529
1558-1721
DOI:10.1109/TR.2017.2669090