3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration

A Field Programmable Gate Array (FPGA) family was designed to match a programmable fabric die built in 14nm process technology with 28Gb/s transceiver dice. The 2.5D packaging (Fig. 3.3.1) uses embedded interconnect bridges (EMIB) [1]. 20nm transceivers were reused enabling a transceiver roadmap ind...

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Bibliographic Details
Main Authors: Greenhill, David, Ho, Ron, Lewis, David, Schmit, Herman, Kok Hong Chan, Tong, Andy, Atsatt, Sean, How, Dana, McElheny, Peter, Duwel, Keith, Schulz, Jeffrey, Faulkner, Darren, Iyer, Gopal, Chen, George, Hee Kong Phoon, Han Wooi Lim, Wei-Yee Koay, Garibay, Ty
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Fabrics
Field programmable gate arrays
Integrated circuit interconnections
Routing
Transceivers
Transistors
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Summary:A Field Programmable Gate Array (FPGA) family was designed to match a programmable fabric die built in 14nm process technology with 28Gb/s transceiver dice. The 2.5D packaging (Fig. 3.3.1) uses embedded interconnect bridges (EMIB) [1]. 20nm transceivers were reused enabling a transceiver roadmap independent of FPGA fabric. Fig. 3.3.2 shows a 560mm 2 fabric die and six transceiver dice. The programmable fabric contains 2.8M logic elements, DSP, memory components, and routing interconnect operating at up to 1GHz. Applications drove the need for improved flexibility and security of the FPGA configuration system. A triple-modular redundant microprocessor-based secure device manager (SDM) was designed and is programmed by embedded software.
ISSN:2376-8606
DOI:10.1109/ISSCC.2017.7870257