3.7 A 1920×1080 30fps 2.3TOPS/W stereo-depth processor for robust autonomous navigation

This paper presents a stereo vision processor that fully implements the SGM algorithm on a single chip. The design uses a new image-scanning stride to enable a deeply pipelined implementation with ultra-wide (1612b) custom SRAM for 1.64Tb/s on-chip access bandwidth. Our design is the first ASIC to r...

Full description

Saved in:
Bibliographic Details
Main Authors: Ziyun Li, Qing Dong, Saligane, Mehdi, Kempke, Benjamin, Shijia Yang, Zhengya Zhang, Dreslinski, Ronald, Sylvester, Dennis, Blaauw, David, Hun Seok Kim
Format: Conference Proceeding
Language:English
Subjects:
Bandwidth
High definition video
Image resolution
Memory management
Program processors
Random access memory
Real-time systems
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper presents a stereo vision processor that fully implements the SGM algorithm on a single chip. The design uses a new image-scanning stride to enable a deeply pipelined implementation with ultra-wide (1612b) custom SRAM for 1.64Tb/s on-chip access bandwidth. Our design is the first ASIC to report performance under the industrial standard KITTI benchmark that renders realistic automobile scenes. The proposed design supports 512-level depth resolution on full HD (1920×1080) resolution with real-time 30fps, consuming 836mW from a 0.75V supply in 40nm CMOS. We also integrate the stereo chip with a quadcopter and demonstrate its operation in real-time flight.
ISSN:2376-8606
DOI:10.1109/ISSCC.2017.7870261