Planarization of dual-damascene post-metal-CMP structures

• Main Authors: Chenting Lin, Clevenger, L., Schnabel, F., Fen Fen Jamin, Dobuzinski, D.
• Format: Conference Proceeding
• Language: English
• Subjects: Applied sciences; Design. Technologies. Operation analysis. Testing; Dielectrics; Electric resistance; Electronics; Etching; Exact sciences and technology; Integrated circuits; Lithography; Metallization, contacts, interconnects; device isolation; Microelectronic fabrication (materials and surfaces technology); Microelectronics; Microelectronics: LSI, VLSI, ULSI; integrated circuit fabrication technology; Planarization; Random access memory; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Slurries; Surface resistance; Surface topography
• DOI: 10.1109/IITC.1999.787086

Metal CMP of dual damascene structures can result in localized topography being introduced into a chip by metal dishing and oxide erosion. The higher the local metal pattern factor, the larger the amount of topography introduced during CMP. This work investigates methods to reduce this additional topography. In our approach, a deeper damascene trench than required is etched and then filled with metal. Then, immediately following metal CMP, the metal CMP slurry flow is stopped and a slurry targeted for oxide removal is introduced to planarize the areas with high metal pattern factors. This planarization CMP procedure reduces the surface topography created during metal CMP and introduces additional metal loss. The additional metal loss is compensated by the deeper damascene trenches. Using this approach, step height and electrical analysis confirm large reductions in topography without an increase in the targeted sheet resistance.