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Top-Gate Electric-Double-Layer IZO-Based Synaptic Transistors for Neuron Networks
In this letter, top-gate electric-double- layer (EDL) indium-zinc-oxide (IZO)-based synaptic transistors were demonstrated. A silicon oxide solid electrolyte film was used as the insulator, which was deposited by the plasma-enhanced chemical vapor deposition method at room temperature. A low operati...
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Published in: | IEEE electron device letters 2017-05, Vol.38 (5), p.588-591 |
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Main Authors: | , , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
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Summary: | In this letter, top-gate electric-double- layer (EDL) indium-zinc-oxide (IZO)-based synaptic transistors were demonstrated. A silicon oxide solid electrolyte film was used as the insulator, which was deposited by the plasma-enhanced chemical vapor deposition method at room temperature. A low operation voltage of 1 V was achieved due to the formation of the EDL layer at the SiO 2 /IZO interface. In the top-gate synaptic transistors, paired-pulse facilitation and high-frequency filter were mimicked, which are the short-term synaptic behaviors. Standard microfabrication processes were used to pattern, which could be used for large integration in the future. |
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ISSN: | 0741-3106 1558-0563 |
DOI: | 10.1109/LED.2017.2690278 |