Impact Analysis On A Memory Hierarchy Applied To IPNoSys Architecture

• Published in: Revista IEEE América Latina 2017-04, Vol.15 (4), p.619-625
• Main Authors: Lima Damasceno, Alexandro, Roberto Fernandes, Silvio, Girao Barreto da Silva, Gustavo
• Format: Article
• Language: English
• Subjects: Access time; Computer architecture; Computer memory; Data storage; Delay; Delays; Graphics processing units; IEEE transactions; Impact analysis; IPNoSys; Low cost; Memory architecture; Memory devices; Memory Hierarchy; Memory management; NOC; Organizations; Random access memory; Storage capacity; Unconventional Architecture
• ISSN: 1548-0992; 1548-0992
• DOI: 10.1109/TLA.2017.7896346

This paper describes a memory hierarchy model proposed for an unconventional architecture called IPNoSys. With memory hierarchy is possible to obtain organizations with low cost, high-speed and large storage capacity. An eficient memory hierarchy application decreases the average access time to memory devices. The IPNoSys architecture have a large fraction of the time spent to treat instructions of memory access. The goal of this work is to analyze the impacts of the application of a memory hierarchy on architecture IPNoSys. With the results, it was observed that in fact the application of the new memory model proved to be efficient and can reduce the memory access delay by 4 times. It was also found that in applications with strong spatial locality and temporal impact is even greater. Finally, it is noted that the factor "number of words per block" directly affects the memory access delay, since the larger the number of words in a block, the higher the hit ratio to the cache and the lower the amount of access to the main memory which is slower.