Efficient SAT-based generation of hazard-activated TSOF tests

With an increasing number of complex cells in today's VLSI designs, intra-gate opens are becoming a larger and larger problem. Typically, these defects are modeled by transistor stuck-off faults (TSOF) and assumed to be detected by transition delay fault (TDF) timing tests. However, tests for T...

Full description

Saved in:
Bibliographic Details
Main Authors: Burchard, Jan, Erb, Dominik, Reddy, Sudhakar M., Singh, Adit D., Becker, Bernd
Format: Conference Proceeding
Language:English
Subjects:
Circuit faults
Delays
Hazards
Libraries
Logic gates
Transistors
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:With an increasing number of complex cells in today's VLSI designs, intra-gate opens are becoming a larger and larger problem. Typically, these defects are modeled by transistor stuck-off faults (TSOF) and assumed to be detected by transition delay fault (TDF) timing tests. However, tests for TDF fail to detect a high percentage of TSOFs and even tools that target them directly are not sufficient to screen all open defects. This is because CMOS circuits experience a large number of hazards during circuit inputs switching which are not modeled by classical tools. Hazards may activate some TSO faults considered untestable by classical ATPGs. The generation of tests that target such hazard activated opens can result in a very significant DPPM improvement - if used. In this paper, we present the first deterministic methodology for targeting hazard activated opens. It is based on a waveform-accurate SAT-based modeling and allows to accurately determine if a TSOF is detectable by hazard activation - or not. In addition, we provide a thorough investigation of the additionally achievable fault coverage using the state-of-the-art NanGate 45nm as well as NanGate 15nm cell libraries.
ISSN:2375-1053
DOI:10.1109/VTS.2017.7928943