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TDDB in HfSiON/SiO2 dielectric stack: Büttiker probe based NEGF modeling, prediction and experiment
HfO2 based high-κ metal gate (HKMG) transistors offer low leakage current and high integration density. However, they are vulnerable to defect formation. In this paper, we have demonstrated a Büttiker probe based leakage current model [1][2] for determining the gate leakage current in a HKMG transi...
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creator | Reza, Ahmed Kamal Hassan, Mohammad Khaled Roy, Kaushik Patra, Devyani Bansal, Ankita Yu Cao |
description | HfO2 based high-κ metal gate (HKMG) transistors offer low leakage current and high integration density. However, they are vulnerable to defect formation. In this paper, we have demonstrated a Büttiker probe based leakage current model [1][2] for determining the gate leakage current in a HKMG transistor due to defects in the gate dielectric layer. These defects can be pre-existing defects (PEDs) as well as the stress induced defects in the gate dielectric stack. The model was also used to determine the post breakdown gate current characteristics. We have verified our model with experimentally measured data from 28nm planar devices with HfSiON/SiO 2 gate dielectric layer. In addition, we have integrated the Büttiker probe method and percolation model [3] to predict the time to failure (t BD ) of the device. The proposed simulation methodology can also be used to determine the required stress condition (SC) to observe breakdown in a device within a certain period of time. |
doi_str_mv | 10.1109/IRPS.2017.7936362 |
format | conference_proceeding |
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However, they are vulnerable to defect formation. In this paper, we have demonstrated a Büttiker probe based leakage current model [1][2] for determining the gate leakage current in a HKMG transistor due to defects in the gate dielectric layer. These defects can be pre-existing defects (PEDs) as well as the stress induced defects in the gate dielectric stack. The model was also used to determine the post breakdown gate current characteristics. We have verified our model with experimentally measured data from 28nm planar devices with HfSiON/SiO 2 gate dielectric layer. In addition, we have integrated the Büttiker probe method and percolation model [3] to predict the time to failure (t BD ) of the device. The proposed simulation methodology can also be used to determine the required stress condition (SC) to observe breakdown in a device within a certain period of time.</description><identifier>EISSN: 1938-1891</identifier><identifier>EISBN: 9781509066414</identifier><identifier>EISBN: 1509066411</identifier><identifier>DOI: 10.1109/IRPS.2017.7936362</identifier><language>eng</language><publisher>IEEE</publisher><subject>Breakdown Prediction ; Büttiker probe ; Dielectrics ; Electric breakdown ; HfSiON ; high-κ metal gate (HKMG) ; Logic gates ; Non-equilibrium Green's function (NEGF) ; Probes ; Stress ; Stress Induced Leakage Current (SILC) ; Temperature ; Temperature Stress ; Time dependent Dielectric Breakdown (TDDB) ; Tunneling ; Voltage Stress ; Weibull</subject><ispartof>2017 IEEE International Reliability Physics Symposium (IRPS), 2017, p.DG-5.1-DG-5.6</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7936362$$EHTML$$P50$$Gieee$$H</linktohtml><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/7936362$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Reza, Ahmed Kamal</creatorcontrib><creatorcontrib>Hassan, Mohammad Khaled</creatorcontrib><creatorcontrib>Roy, Kaushik</creatorcontrib><creatorcontrib>Patra, Devyani</creatorcontrib><creatorcontrib>Bansal, Ankita</creatorcontrib><creatorcontrib>Yu Cao</creatorcontrib><title>TDDB in HfSiON/SiO2 dielectric stack: Büttiker probe based NEGF modeling, prediction and experiment</title><title>2017 IEEE International Reliability Physics Symposium (IRPS)</title><addtitle>IRPS</addtitle><description>HfO2 based high-κ metal gate (HKMG) transistors offer low leakage current and high integration density. However, they are vulnerable to defect formation. In this paper, we have demonstrated a Büttiker probe based leakage current model [1][2] for determining the gate leakage current in a HKMG transistor due to defects in the gate dielectric layer. These defects can be pre-existing defects (PEDs) as well as the stress induced defects in the gate dielectric stack. The model was also used to determine the post breakdown gate current characteristics. We have verified our model with experimentally measured data from 28nm planar devices with HfSiON/SiO 2 gate dielectric layer. In addition, we have integrated the Büttiker probe method and percolation model [3] to predict the time to failure (t BD ) of the device. The proposed simulation methodology can also be used to determine the required stress condition (SC) to observe breakdown in a device within a certain period of time.</description><subject>Breakdown Prediction</subject><subject>Büttiker probe</subject><subject>Dielectrics</subject><subject>Electric breakdown</subject><subject>HfSiON</subject><subject>high-κ metal gate (HKMG)</subject><subject>Logic gates</subject><subject>Non-equilibrium Green's function (NEGF)</subject><subject>Probes</subject><subject>Stress</subject><subject>Stress Induced Leakage Current (SILC)</subject><subject>Temperature</subject><subject>Temperature Stress</subject><subject>Time dependent Dielectric Breakdown (TDDB)</subject><subject>Tunneling</subject><subject>Voltage Stress</subject><subject>Weibull</subject><issn>1938-1891</issn><isbn>9781509066414</isbn><isbn>1509066411</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2017</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotkM1OAjEUhauJiYg8gHHTB3Dg3rbTad3JPwkBI7gmZXprKjCQmS703dz5YpLI5pzFl5wvOYw9IHQRwfZmb6-rrgAsuoWVWmpxxTq2MJiDBa0VqmvWQitNhsbiLbtrmk8AAdLoFvPr4bDPY8WnYRWXi945BPeR9lSmOpa8Sa7cPfP-709KcUc1P9XHLfGta8jzxWgy5oejp32sPp7OiHwsUzxW3FWe09eJ6nigKt2zm-D2DXUu3Wbv49F6MM3my8ls8DLPIhZ5yryCUAajTMiLkEuE3LmwRU3opHIAJSoDwiopvQ_CWIeYOw0FkpC-kEq22eP_biSizeksd_X35nKK_APxZ1UM</recordid><startdate>201704</startdate><enddate>201704</enddate><creator>Reza, Ahmed Kamal</creator><creator>Hassan, Mohammad Khaled</creator><creator>Roy, Kaushik</creator><creator>Patra, Devyani</creator><creator>Bansal, Ankita</creator><creator>Yu Cao</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201704</creationdate><title>TDDB in HfSiON/SiO2 dielectric stack: Büttiker probe based NEGF modeling, prediction and experiment</title><author>Reza, Ahmed Kamal ; Hassan, Mohammad Khaled ; Roy, Kaushik ; Patra, Devyani ; Bansal, Ankita ; Yu Cao</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-d40fcf848f57f53105aafb16e1a34a00c148029433ddf289a115a6071e23d7343</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2017</creationdate><topic>Breakdown Prediction</topic><topic>Büttiker probe</topic><topic>Dielectrics</topic><topic>Electric breakdown</topic><topic>HfSiON</topic><topic>high-κ metal gate (HKMG)</topic><topic>Logic gates</topic><topic>Non-equilibrium Green's function (NEGF)</topic><topic>Probes</topic><topic>Stress</topic><topic>Stress Induced Leakage Current (SILC)</topic><topic>Temperature</topic><topic>Temperature Stress</topic><topic>Time dependent Dielectric Breakdown (TDDB)</topic><topic>Tunneling</topic><topic>Voltage Stress</topic><topic>Weibull</topic><toplevel>online_resources</toplevel><creatorcontrib>Reza, Ahmed Kamal</creatorcontrib><creatorcontrib>Hassan, Mohammad Khaled</creatorcontrib><creatorcontrib>Roy, Kaushik</creatorcontrib><creatorcontrib>Patra, Devyani</creatorcontrib><creatorcontrib>Bansal, Ankita</creatorcontrib><creatorcontrib>Yu Cao</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Reza, Ahmed Kamal</au><au>Hassan, Mohammad Khaled</au><au>Roy, Kaushik</au><au>Patra, Devyani</au><au>Bansal, Ankita</au><au>Yu Cao</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>TDDB in HfSiON/SiO2 dielectric stack: Büttiker probe based NEGF modeling, prediction and experiment</atitle><btitle>2017 IEEE International Reliability Physics Symposium (IRPS)</btitle><stitle>IRPS</stitle><date>2017-04</date><risdate>2017</risdate><spage>DG-5.1</spage><epage>DG-5.6</epage><pages>DG-5.1-DG-5.6</pages><eissn>1938-1891</eissn><eisbn>9781509066414</eisbn><eisbn>1509066411</eisbn><abstract>HfO2 based high-κ metal gate (HKMG) transistors offer low leakage current and high integration density. However, they are vulnerable to defect formation. In this paper, we have demonstrated a Büttiker probe based leakage current model [1][2] for determining the gate leakage current in a HKMG transistor due to defects in the gate dielectric layer. These defects can be pre-existing defects (PEDs) as well as the stress induced defects in the gate dielectric stack. The model was also used to determine the post breakdown gate current characteristics. We have verified our model with experimentally measured data from 28nm planar devices with HfSiON/SiO 2 gate dielectric layer. In addition, we have integrated the Büttiker probe method and percolation model [3] to predict the time to failure (t BD ) of the device. The proposed simulation methodology can also be used to determine the required stress condition (SC) to observe breakdown in a device within a certain period of time.</abstract><pub>IEEE</pub><doi>10.1109/IRPS.2017.7936362</doi></addata></record> |
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subjects | Breakdown Prediction Büttiker probe Dielectrics Electric breakdown HfSiON high-κ metal gate (HKMG) Logic gates Non-equilibrium Green's function (NEGF) Probes Stress Stress Induced Leakage Current (SILC) Temperature Temperature Stress Time dependent Dielectric Breakdown (TDDB) Tunneling Voltage Stress Weibull |
title | TDDB in HfSiON/SiO2 dielectric stack: Büttiker probe based NEGF modeling, prediction and experiment |
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