Robust test pattern generation for hold-time faults in nanometer technologies

Hold-time faults are gaining attention in modern technologies because of process variation, power supply noise, and etc. A path-based hold-time fault model is proposed to cover short paths to and from every flip-flop. In addition, the number of faults is linear to the number of flip-flops in the cir...

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Bibliographic Details
Main Authors: Yu-Hao Ho, Yo-Wei Chen, Chih-Ming Chang, Kai-Chieh Yang, Li, James Chien-Mo
Format: Conference Proceeding
Language:English
Subjects:
ATPG
Circuit faults
Clocks
Delays
Fault Model
Fault Simulation
Flip-flops
Hold-time Test
Integrated circuit modeling
Logic gates
Robustness
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Summary:Hold-time faults are gaining attention in modern technologies because of process variation, power supply noise, and etc. A path-based hold-time fault model is proposed to cover short paths to and from every flip-flop. In addition, the number of faults is linear to the number of flip-flops in the circuit. Two-timeframe circuit models are proposed for ATPG and fault simulation. We show that traditional path delay fault ATPG is not sufficient for hold-time faults. A hold-time fault ATPG is presented to generate robust test patterns. Experiments on large benchmark show that our test patterns are 42% shorter while 38% better in robust fault coverage than 1-detect stuck-at fault test sets. The results justify the need for hold-time fault ATPG.
ISSN:2472-9124
DOI:10.1109/VLSI-DAT.2017.7939647