Design of efficient SPARC cores for embedded systems

The paper reports on design decisions taken in the modelling, design and implementation of a full set of SPARC v8 Integer Unit versions and gives data about the experimental results obtained. VHDL was the description language, Synopsys tools were for the logical synthesis, and Duet Technologies'...

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Bibliographic Details
Main Authors: Bautista, T., Nunez, A.
Format: Conference Proceeding
Language:English
Subjects:
Application software
Clocks
Coprocessors
Costs
Electronic design automation and methodology
Embedded system
Energy consumption
Instruction sets
Microarchitecture
Space technology
Online Access:Request full text
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Summary:The paper reports on design decisions taken in the modelling, design and implementation of a full set of SPARC v8 Integer Unit versions and gives data about the experimental results obtained. VHDL was the description language, Synopsys tools were for the logical synthesis, and Duet Technologies' Epoch was used for the physical layout of the final circuits. These have been carried out in a 0.35 /spl mu/m, three-metal layer CMOS process. The description strategy and the design flow methodology allow us to obtain quantitative results that characterize suitable points in the design space. They show how much microarchitecture, design, datapath granularity and module decisions affect performance and cost functions. This design space exploration down to physical layouts is made possible by modelling techniques based on configurable VHDL descriptions.
ISSN:1089-6503
2376-9505
DOI:10.1109/EURMIC.1999.794473