A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection

• Published in: IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2018-03, Vol.65 (3), p.376-380
• Main Authors: Aranda, Luis Alberto, Reviriego, Pedro, Maestro, Juan Antonio
• Format: Article
• Language: English
• Subjects: Circuit faults; concurrent error detection; Digital signal processing; Dual modular redundancy; fault injection; Field programmable gate arrays; finite impulse response filter; Finite impulse response filters; IP networks; Redundancy; SRAM-based FPGA
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2017.2717490

Compared with application specific integrated circuits (ASICs), static random access memory (SRAM)-based field programmable gate arrays (FPGAs) respond differently to radiation due to the configuration memory vulnerability. In this brief, the differences between the permanent error model for SRAM-based FPGAs due to configuration memory single event upsets (SEUs), and the ASIC SEU error model are put into perspective for error detection schemes. In particular, a concurrent error detection (CED) technique for finite impulse response filters in ASICs is implemented and evaluated in an SRAM-based FPGA through fault injection emulation. This method is compared with a dual modular redundancy (DMR) scheme in order to obtain a common behavior. The analysis of experimental data indicates that the CED technique has less undetected errors than DMR. However, our exhaustive fault injection tests reveal that false positive detections are more likely to occur in CED, since the error detection branch uses more FPGA resources than the DMR comparator. This phenomenon, which is negligible in ASICs, implies a partial or complete unnecessary reconfiguration, so it should be considered in SRAM-based FPGAs.