Bi-directional flip-chip 28 GHz phased-array core-chip in 45nm CMOS SOI for high-efficiency high-linearity 5G systems

This paper presents a 0 mW two-channel 28 GHz bi-directional phased-array chip packaged using flip-chip interconnects in 45nm CMOS SOI. The design alternates switched-LC phase shifters with switched attenuators to result in 5-bit phase control with an rms gain and phase error

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Bibliographic Details
Main Authors: Kodak, Umut, Rebeiz, Gabriel M.
Format: Conference Proceeding
Language:English
Subjects:
Base-Stations
Bidirectional control
CMOS SOI
Gain
Gain measurement
Gallium arsenide
Noise measurement
Phase measurement
Phased arrays
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Description
Summary:This paper presents a 0 mW two-channel 28 GHz bi-directional phased-array chip packaged using flip-chip interconnects in 45nm CMOS SOI. The design alternates switched-LC phase shifters with switched attenuators to result in 5-bit phase control with an rms gain and phase error
ISSN:2375-0995
DOI:10.1109/RFIC.2017.7969017