Method and structure to reduce leakage for ESD device: ET/ID: Enabling technologies and innovative devices

To fully enable and leverage the power of advanced processors, products must have abundant cache memory with much shorter access paths without increasing chip power for nonfunctional cells such as such as electrostatic discharge (ESD) circuits. It is very critical to have ESD circuits to protect the...

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Bibliographic Details
Main Authors: Ginawi, Ahmed Y., Habib, Nazmul, Muhammad, Mujahid, Bickford, Jeanne P.
Format: Conference Proceeding
Language:English
Subjects:
Clamps
Discharges (electric)
Electrostatic Discharge Device
Electrostatic discharges
Field effect transistors
Logic gates
Manufacturing
Stacked Chips
Systems operation
Trap Charge Device
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Summary:To fully enable and leverage the power of advanced processors, products must have abundant cache memory with much shorter access paths without increasing chip power for nonfunctional cells such as such as electrostatic discharge (ESD) circuits. It is very critical to have ESD circuits to protect the chip and module but also important to ensure that ESD circuits don't add significant power to the chip. A novel solution to meet higher ESD requirements during chip manufacturing, packaging, and test that can be "turned off" in system operation to reduce power is described.
ISSN:2376-6697
DOI:10.1109/ASMC.2017.7969276