Stacked Keeper with Body Bias Approach to Reduce Leakage Power for 2-Byte CAM Using 180NM CMOS Technology

Over the past few decades, the designers concentrating on different techniques to design low power chips. The power consumption can be reduced by minimizing the leakage power and leakage current in that specified design. Power consumption is main criteria in digital memory circuits, to reduce and to...

Full description

Saved in:
Bibliographic Details
Main Authors: Naresh, K., Madhavarao, V., Sravanthi, M. Kavitha, Ratnam, M. Rohith Anath
Format: Conference Proceeding
Language:English
Subjects:
body biasing
CAM
CMOS technology
Computer architecture
Inverters
leakage power
Microprocessors
MOS devices
Power demand
SKBB
Transistors
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by
cites
container_end_page 525
container_issue
container_start_page 520
container_title
container_volume
creator Naresh, K.
Madhavarao, V.
Sravanthi, M. Kavitha
Ratnam, M. Rohith Anath
description Over the past few decades, the designers concentrating on different techniques to design low power chips. The power consumption can be reduced by minimizing the leakage power and leakage current in that specified design. Power consumption is main criteria in digital memory circuits, to reduce and to recover the power, we have many techniques are available. A Stacked Keeper Body Bias (SKBB) is one of the technique is applied to the conditional circuitry of the memory block. The modification and replacements were done in the conditional circuitry. The Bit Line, Write Line decoder, Priority Encoder was used to design efficient 2Byte CAM. The result shows that it is dissipating 50% less power than the conventional CAM Design.
doi_str_mv 10.1109/IACC.2017.0113
format conference_proceeding
fullrecord <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_7976847</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>7976847</ieee_id><sourcerecordid>7976847</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-5782384f3d3b6e70feb9803b4e3d7d44b4ff34385959f887a6bbeeef2eee89b93</originalsourceid><addsrcrecordid>eNotkM1OwkAYRUcTExHZunHzvUBxfjszy9L4QwQxgmsy034DFWSatob07W2im3uTk5uzuITcMTpljNqHeZbnU06ZnlLGxAW5YYpaylRK5SUZcalFIpRm12TStl-UUpZyzrUakWrdueKAJbwi1tjAuer2MItlD7PKtZDVdRNdsYcuwgeWPwXCAt3B7RDe43nYh9gAT2Z9h5BnS_hsq9MOmKFvS8iXqzVssNif4jHu-ltyFdyxxcl_j8nm6XGTvySL1fM8zxZJZWmXKG24MDKIUvgUNQ3oraHCSxSlLqX0MgQhhVFW2WCMdqn3iBj4EMZ6K8bk_k9bDWRbN9W3a_qttjo1wwu_XKxUxA</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Stacked Keeper with Body Bias Approach to Reduce Leakage Power for 2-Byte CAM Using 180NM CMOS Technology</title><source>IEEE Xplore All Conference Series</source><creator>Naresh, K. ; Madhavarao, V. ; Sravanthi, M. Kavitha ; Ratnam, M. Rohith Anath</creator><creatorcontrib>Naresh, K. ; Madhavarao, V. ; Sravanthi, M. Kavitha ; Ratnam, M. Rohith Anath</creatorcontrib><description>Over the past few decades, the designers concentrating on different techniques to design low power chips. The power consumption can be reduced by minimizing the leakage power and leakage current in that specified design. Power consumption is main criteria in digital memory circuits, to reduce and to recover the power, we have many techniques are available. A Stacked Keeper Body Bias (SKBB) is one of the technique is applied to the conditional circuitry of the memory block. The modification and replacements were done in the conditional circuitry. The Bit Line, Write Line decoder, Priority Encoder was used to design efficient 2Byte CAM. The result shows that it is dissipating 50% less power than the conventional CAM Design.</description><identifier>EISSN: 2473-3571</identifier><identifier>EISBN: 1509015604</identifier><identifier>EISBN: 9781509015603</identifier><identifier>DOI: 10.1109/IACC.2017.0113</identifier><identifier>CODEN: IEEPAD</identifier><language>eng</language><publisher>IEEE</publisher><subject>body biasing ; CAM ; CMOS technology ; Computer architecture ; Inverters ; leakage power ; Microprocessors ; MOS devices ; Power demand ; SKBB ; Transistors</subject><ispartof>2017 IEEE 7th International Advance Computing Conference (IACC), 2017, p.520-525</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7976847$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,23911,23912,25120,27904,54533,54910</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/7976847$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Naresh, K.</creatorcontrib><creatorcontrib>Madhavarao, V.</creatorcontrib><creatorcontrib>Sravanthi, M. Kavitha</creatorcontrib><creatorcontrib>Ratnam, M. Rohith Anath</creatorcontrib><title>Stacked Keeper with Body Bias Approach to Reduce Leakage Power for 2-Byte CAM Using 180NM CMOS Technology</title><title>2017 IEEE 7th International Advance Computing Conference (IACC)</title><addtitle>IADCC</addtitle><description>Over the past few decades, the designers concentrating on different techniques to design low power chips. The power consumption can be reduced by minimizing the leakage power and leakage current in that specified design. Power consumption is main criteria in digital memory circuits, to reduce and to recover the power, we have many techniques are available. A Stacked Keeper Body Bias (SKBB) is one of the technique is applied to the conditional circuitry of the memory block. The modification and replacements were done in the conditional circuitry. The Bit Line, Write Line decoder, Priority Encoder was used to design efficient 2Byte CAM. The result shows that it is dissipating 50% less power than the conventional CAM Design.</description><subject>body biasing</subject><subject>CAM</subject><subject>CMOS technology</subject><subject>Computer architecture</subject><subject>Inverters</subject><subject>leakage power</subject><subject>Microprocessors</subject><subject>MOS devices</subject><subject>Power demand</subject><subject>SKBB</subject><subject>Transistors</subject><issn>2473-3571</issn><isbn>1509015604</isbn><isbn>9781509015603</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2017</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotkM1OwkAYRUcTExHZunHzvUBxfjszy9L4QwQxgmsy034DFWSatob07W2im3uTk5uzuITcMTpljNqHeZbnU06ZnlLGxAW5YYpaylRK5SUZcalFIpRm12TStl-UUpZyzrUakWrdueKAJbwi1tjAuer2MItlD7PKtZDVdRNdsYcuwgeWPwXCAt3B7RDe43nYh9gAT2Z9h5BnS_hsq9MOmKFvS8iXqzVssNif4jHu-ltyFdyxxcl_j8nm6XGTvySL1fM8zxZJZWmXKG24MDKIUvgUNQ3oraHCSxSlLqX0MgQhhVFW2WCMdqn3iBj4EMZ6K8bk_k9bDWRbN9W3a_qttjo1wwu_XKxUxA</recordid><startdate>201701</startdate><enddate>201701</enddate><creator>Naresh, K.</creator><creator>Madhavarao, V.</creator><creator>Sravanthi, M. Kavitha</creator><creator>Ratnam, M. Rohith Anath</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201701</creationdate><title>Stacked Keeper with Body Bias Approach to Reduce Leakage Power for 2-Byte CAM Using 180NM CMOS Technology</title><author>Naresh, K. ; Madhavarao, V. ; Sravanthi, M. Kavitha ; Ratnam, M. Rohith Anath</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-5782384f3d3b6e70feb9803b4e3d7d44b4ff34385959f887a6bbeeef2eee89b93</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2017</creationdate><topic>body biasing</topic><topic>CAM</topic><topic>CMOS technology</topic><topic>Computer architecture</topic><topic>Inverters</topic><topic>leakage power</topic><topic>Microprocessors</topic><topic>MOS devices</topic><topic>Power demand</topic><topic>SKBB</topic><topic>Transistors</topic><toplevel>online_resources</toplevel><creatorcontrib>Naresh, K.</creatorcontrib><creatorcontrib>Madhavarao, V.</creatorcontrib><creatorcontrib>Sravanthi, M. Kavitha</creatorcontrib><creatorcontrib>Ratnam, M. Rohith Anath</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library Online</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Naresh, K.</au><au>Madhavarao, V.</au><au>Sravanthi, M. Kavitha</au><au>Ratnam, M. Rohith Anath</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Stacked Keeper with Body Bias Approach to Reduce Leakage Power for 2-Byte CAM Using 180NM CMOS Technology</atitle><btitle>2017 IEEE 7th International Advance Computing Conference (IACC)</btitle><stitle>IADCC</stitle><date>2017-01</date><risdate>2017</risdate><spage>520</spage><epage>525</epage><pages>520-525</pages><eissn>2473-3571</eissn><eisbn>1509015604</eisbn><eisbn>9781509015603</eisbn><coden>IEEPAD</coden><abstract>Over the past few decades, the designers concentrating on different techniques to design low power chips. The power consumption can be reduced by minimizing the leakage power and leakage current in that specified design. Power consumption is main criteria in digital memory circuits, to reduce and to recover the power, we have many techniques are available. A Stacked Keeper Body Bias (SKBB) is one of the technique is applied to the conditional circuitry of the memory block. The modification and replacements were done in the conditional circuitry. The Bit Line, Write Line decoder, Priority Encoder was used to design efficient 2Byte CAM. The result shows that it is dissipating 50% less power than the conventional CAM Design.</abstract><pub>IEEE</pub><doi>10.1109/IACC.2017.0113</doi><tpages>6</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier EISSN: 2473-3571
ispartof 2017 IEEE 7th International Advance Computing Conference (IACC), 2017, p.520-525
issn 2473-3571
language eng
recordid cdi_ieee_primary_7976847
source IEEE Xplore All Conference Series
subjects body biasing
CAM
CMOS technology
Computer architecture
Inverters
leakage power
Microprocessors
MOS devices
Power demand
SKBB
Transistors
title Stacked Keeper with Body Bias Approach to Reduce Leakage Power for 2-Byte CAM Using 180NM CMOS Technology
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-27T17%3A58%3A29IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Stacked%20Keeper%20with%20Body%20Bias%20Approach%20to%20Reduce%20Leakage%20Power%20for%202-Byte%20CAM%20Using%20180NM%20CMOS%20Technology&rft.btitle=2017%20IEEE%207th%20International%20Advance%20Computing%20Conference%20(IACC)&rft.au=Naresh,%20K.&rft.date=2017-01&rft.spage=520&rft.epage=525&rft.pages=520-525&rft.eissn=2473-3571&rft.coden=IEEPAD&rft_id=info:doi/10.1109/IACC.2017.0113&rft.eisbn=1509015604&rft.eisbn_list=9781509015603&rft_dat=%3Cieee_CHZPO%3E7976847%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i90t-5782384f3d3b6e70feb9803b4e3d7d44b4ff34385959f887a6bbeeef2eee89b93%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=7976847&rfr_iscdi=true