MASI: An eviction aware cache coherence protocol for CMPs

This work proposes a novel 4-state cache coherence protocol that ensures better efficiency in Chip Multiprocessors (CMPs) compared to that of conventional 4 and 5-state protocols, e.g. MESI/MOESI. The proposed MASI coherence protocol realizes judicious cache line state transition that has considerab...

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Bibliographic Details
Main Authors: Dalui, Mamata, Som, Tannishtha, Bansal, Shivani, Pant, Shivam, Sikdar, Biplab K.
Format: Conference Proceeding
Language:English
Subjects:
Cache coherence
chip multiprocessors
Coherence
directory based system
eviction of data block
Indexes
MASI protocol
Oceans
Ports (Computers)
Programming
Protocols
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Summary:This work proposes a novel 4-state cache coherence protocol that ensures better efficiency in Chip Multiprocessors (CMPs) compared to that of conventional 4 and 5-state protocols, e.g. MESI/MOESI. The proposed MASI coherence protocol realizes judicious cache line state transition that has considerable impact on the reduction in number of data block forwarding. Its feature is to keep trace of the eviction of data block from the upper level cache. It further brings down the overhead of writeback. The simulation results establish the effectiveness of the MASI protocol for a directory based system that is conventionally employed for large scale CMPs.
ISSN:2473-9413
DOI:10.1109/ISED.2016.7977091