A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors

As minimum area SRAM bit-cells are obtained when using cell ratio and pull-up ratio of 1, we analyze the possibility of decreasing the cell ratio from the conventional values comprised between 1.5-2.5 to 1. The impact of this option on area, power, performance and stability is analyzed showing that...

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Bibliographic Details
Published in:IEEE transactions on emerging topics in computing 2019-07, Vol.7 (3), p.447-455
Main Authors: Torrens, Gabriel, Alorda, Bartomeu, Carmona, Cristian, Malagon-Perianez, Daniel, Segura, Jaume, Bota, Sebastia
Format: Article
Language:English
Subjects:
6T-SRAM
Circuit reliability
Circuit stability
CMOS
CMOS embedded SRAM
Energy dissipation
Inverters
Layout
Leakage current
Reduction
Semiconductor devices
Soft errors
SRAM
SRAM cells
Stability analysis
Static random access memory
Transistors
Vt variability
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Summary:As minimum area SRAM bit-cells are obtained when using cell ratio and pull-up ratio of 1, we analyze the possibility of decreasing the cell ratio from the conventional values comprised between 1.5-2.5 to 1. The impact of this option on area, power, performance and stability is analyzed showing that the most affected parameter is read stability, although this impact can be overcome using some of the read assist circuits proposed in the literature. The main benefits are layout regularity enhancement, with its consequent higher tolerance to variability, cell area reduction by 25 percent (with respect to a cell having a cell ratio of 2), leakage current improvement by a 35 percent, as well as energy dissipation reduction and a soft error rate per bit improvement of around 30 percent.
ISSN:2168-6750
2168-6750
DOI:10.1109/TETC.2017.2721932