High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension

Screen content coding (SCC) extension to High Efficiency Video Coding (HEVC) offers substantial compression efficiency over the existing HEVC standard for computer generated content. However, this gain in compression efficiency is achieved at the expense of further computational complexity with seve...

Full description

Saved in:
Bibliographic Details
Main Authors: Senanayake, Rishan, Liyanage, Namitha, Wijeratne, Sasindu, Atapattu, Sachille, Athukorala, Kasun, Tharaka, P. M. K., Karunaratne, Geethan, Senarath, R. M. A. U., Perera, Ishantha, Ekanayake, Ashen, Pasqual, Ajith
Format: Conference Proceeding
Language:English
Subjects:
Encoding
Estimation
Hardware
high efficiency video coding
low latency encoding
Random access memory
real time systems
screen content coding
Throughput
Video coding
video coding on fpga
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Screen content coding (SCC) extension to High Efficiency Video Coding (HEVC) offers substantial compression efficiency over the existing HEVC standard for computer generated content. However, this gain in compression efficiency is achieved at the expense of further computational complexity with several resource hungry coding tools. Hence, extension of SCC to HEVC hardware encoders can be challenging. This paper presents resource efficient hardware designs for two key SCC tools, Intra Block Copy and Palette Coding. Moreover, a new hash search approach is proposed for Intra Block Copy, while a hardware friendly palette indices coding scheme is suggested for Palette Coding. These designs are targeted to achieve the throughput necessary for an 1080p 30 frames/s encoder, and incurs coding loss of 11.4% and 5.1% respectively in all intra configurations. The designs are synthesized for a Virtex-7 VC707 evaluation platform.
ISSN:2160-052X
DOI:10.1109/ASAP.2017.7995274