Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging

In this study, the warpage and thermal performances of fan-out wafer-level packaging (FOWLP) are investigated. Emphasis is placed on the characterization of the effects of FOWLP important parameters, such as chip size, chip thickness, package/chip area ratio, epoxy molding compound (EMC), chip EMC c...

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Main Authors: Lau, John, Ming Li, Tian, Dewen, Fan, Nelson, Kuah, Eric, Wu Kai, Li, Margie, Hao, J., Ken Cheung, Zhang Li, Kim Hwee Tan, Beica, Rozalia, Cheng-Ta Ko, Yu-Hua Chen, Sze Pei Lim, Ning Cheng Lee, Koh Sau Wee, Ran, Jiang, Xi, Cao
Format: Conference Proceeding
Language:English
Subjects:
Boundary conditions
Compression molding
Electromagnetic compatibility
Finite element analysis
Packaging
Semiconductor device modeling
Stress
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creator Lau, John
Ming Li
Tian, Dewen
Fan, Nelson
Kuah, Eric
Wu Kai
Li, Margie
Hao, J.
Ken Cheung
Zhang Li
Kim Hwee Tan
Beica, Rozalia
Cheng-Ta Ko
Yu-Hua Chen
Sze Pei Lim
Ning Cheng Lee
Koh Sau Wee
Ran, Jiang
Xi, Cao
description In this study, the warpage and thermal performances of fan-out wafer-level packaging (FOWLP) are investigated. Emphasis is placed on the characterization of the effects of FOWLP important parameters, such as chip size, chip thickness, package/chip area ratio, epoxy molding compound (EMC), chip EMC cap, carrier material and thickness, and die-attach film, on the warpage after post mold cure (PMC) and backgrinding of the EMC. The simulation results are compared with the experimental measurements. Also, the thermal performance (junction-to-ambient thermal resistance) of FOWLP with various chip thicknesses is characterized. Finally, some FOWLP important parameters affecting the warpage and thermal performances are recommended.
doi_str_mv 10.1109/ECTC.2017.309
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ispartof 2017 IEEE 67th Electronic Components and Technology Conference (ECTC), 2017, p.595-602
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source IEEE Xplore All Conference Series
subjects Boundary conditions
Compression molding
Electromagnetic compatibility
Finite element analysis
Packaging
Semiconductor device modeling
Stress
title Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging
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