Analysis of ground-bounce induced substrate noise coupling in a low resistive bulk epitaxial process: design strategies to minimize noise effects on a mixed-signal chip

• Published in: IEEE transactions on circuits and systems. 2, Analog and digital signal processing Analog and digital signal processing, 1999-11, Vol.46 (11), p.1427-1436
• Main Authors: Felder, M., Ganger, J.
• Format: Article
• Language: English
• Subjects: Analytical models; Circuit noise; Circuit simulation; Coupling circuits; Electrical equipment industry; Integrated circuit measurements; Noise measurement; Performance analysis; SPICE; System-on-a-chip
• ISSN: 1057-7130; 1558-125X
• DOI: 10.1109/82.803483

The industry trend toward system-on-chip solutions continues to push the limits of mixed-signal design. Increasing the integration of analog and digital circuitry causes a struggle to maintain analog signal integrity. Digital switching of noise coupling through the common substrate is both difficult to measure and difficult to control. This paper introduces and applies a practical first-order simulation methodology for performing a substrate noise analysis in a low resistive bulk process. Although this subject has been analyzed in numerous journal articles, few have applied their analysis method to a whole-chip design. This SPICE model will allow mixed-signal designers to determine design variables that will minimize substrate noise. This work elaborates on key aspects of substrate noise that available references do not handle adequately, including: sources of substrate noise, determination of power-rail and bulk-resonance frequencies, and alternatives for bulk biasing. The new model is used to analyze Motorola's 56824, the latest low-cost 16-bit digital signal processor design. The analysis includes the determination of: (1) the on-chip bus and I/O bus noise coupled to the substrate; (2) the dominant resonant frequencies in the chip; and (3) the best bulk-biasing alternative.