A high resolution Time-to-Digital Converter (TDC) based on self-calibrated Digital-to-Time Converter (DTC)

Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps~1.4ps resolution and 11ps~22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same...

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Bibliographic Details
Main Authors: Tingbing Ouyang, Bo Wang, Lizhao Gao, Jiangtao Gu, Chao Zhang
Format: Conference Proceeding
Language:English
Subjects:
Calibration
Capacitors
Delay lines
Delays
Digital-to-Time Converter (DTC)
integral nonlinearity (INL)
Inverters
Layout
Linearity
ruler DTC(RDTC)
self-calibration
Time-to-Digital Converter (TDC)
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Summary:Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps~1.4ps resolution and 11ps~22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same time interval among two neighboring DTCs, a highly linear TDC is realized. To avoid the manual tuning, a self-calibration method is proposed, which allows for the calibration after the tape-out. The method utilizes a ruler DTC(RDTC) as the input signal of TDC to calibrate it. After self-calibration, the resolution of TDC is equal to the RDTC's delay step, so the resolution becomes adjustable by altering the RDTC's delay step. Setting the resolution at 1ps, the integral nonlinearity (INL) is 0.07LSB, the power consumption is 1.37mW at 50MHz with a 1.2V operating voltage and it occupies a core area of 0.018 mm 2 in 0.13um CMOS process.
ISSN:1558-3899
DOI:10.1109/MWSCAS.2017.8053013