Noise and non-linearity analysis of a charge-injection-cell-based 10-bit 50-MS/s SAR-ADC

This paper presents a detailed noise and non-linearity analysis of a 10-bit 1.2Vppd 50MS/s charge-injection based SAR-ADC designed in a 65 nm low power process. Being more area-efficient in contrast to a conventional capacitor DAC, a charge-injection-cell-based DAC allows to reuse its DAC cells duri...

Full description

Saved in:
Bibliographic Details
Main Authors: Runge, Marcel, Schmock, Dario, Gerfers, Friedel
Format: Conference Proceeding
Language:English
Subjects:
Capacitors
Jitter
Logic gates
Reservoirs
Switches
Transient analysis
Transistors
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper presents a detailed noise and non-linearity analysis of a 10-bit 1.2Vppd 50MS/s charge-injection based SAR-ADC designed in a 65 nm low power process. Being more area-efficient in contrast to a conventional capacitor DAC, a charge-injection-cell-based DAC allows to reuse its DAC cells during binary search. Based on extensive calculations and transistorlevel simulations, the charge-injection cell design tradeoffs are analyzed and optimized to maximize the overall ADC linearity and ADC input range. Extensive system level simulations in MATLAB evaluate the jitter sensitivity of the ADC. Combining the transistor-level and system level simulations, a detailed noise study of the 8.86-bit ENOB ADC completes the evaluation.
ISSN:1558-3899
DOI:10.1109/MWSCAS.2017.8053101