Towards a standard for embedded core test: an example

Integrated circuits are increasingly designed by embedding pre-designed reusable cores. IEEE P1500 Standard for Embedded Core Test (SECT) is a standard-under-development that aims at improving ease of reuse and facilitating interoperability with respect to the test of such core-based ICs, especially...

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Main Authors: Marinissen, E.J., Zorian, Y., Kapur, R., Taylor, T., Whetsel, L.
Format: Conference Proceeding
Language:English
Subjects:
Circuit faults
Circuit testing
Crosstalk
Hardware
Instruments
Integrated circuit interconnections
Manufacturing
Standardization
Standards development
System testing
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Zorian, Y.
Kapur, R.
Taylor, T.
Whetsel, L.
description Integrated circuits are increasingly designed by embedding pre-designed reusable cores. IEEE P1500 Standard for Embedded Core Test (SECT) is a standard-under-development that aims at improving ease of reuse and facilitating interoperability with respect to the test of such core-based ICs, especially if they contain cores from different sources. This paper briefly describes IEEE P1500, and illustrates through a simplified example its dual compliance concept, its Scalable Hardware Architecture, and its Core Test Language. This paper provides a preliminary, unapproved view on IEEE P1500. The standard is still under development, and this paper only reflects the view of five active participants of the Standardization Committee on its current status.
doi_str_mv 10.1109/TEST.1999.805786
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fullrecord <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_805786</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>805786</ieee_id><sourcerecordid>805786</sourcerecordid><originalsourceid>FETCH-LOGICAL-i87t-b2763f9dc1c9cd50ff6ec4ef14c123a22b1130c71df4ed86593ffe812bafc3e3</originalsourceid><addsrcrecordid>eNotj8tqwzAQAEUfUCftvfSkH7Czq7UsqbcS0gcEcojvQZZW4BLHwTK0_fsW0tPMaWCEeESoEMGt2s2-rdA5V1nQxjZXolBkbKmUhmuxAGOBtNGEN6JAsK4kTe5OLHL-BFCgFRRCt-OXn2KWXubZn-KfyzROkoeOY-QowzixnDnPz9KfJH_74Xzke3Gb_DHzwz-XYv-6adfv5Xb39rF-2Za9NXPZKdNQcjFgcCFqSKnhUHPCOqAir1SHSBAMxlRztI12lBJbVJ1PgZiW4ulS7Zn5cJ76wU8_h8sr_QKJbkZH</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Towards a standard for embedded core test: an example</title><source>IEEE Xplore All Conference Series</source><creator>Marinissen, E.J. ; Zorian, Y. ; Kapur, R. ; Taylor, T. ; Whetsel, L.</creator><creatorcontrib>Marinissen, E.J. ; Zorian, Y. ; Kapur, R. ; Taylor, T. ; Whetsel, L.</creatorcontrib><description>Integrated circuits are increasingly designed by embedding pre-designed reusable cores. IEEE P1500 Standard for Embedded Core Test (SECT) is a standard-under-development that aims at improving ease of reuse and facilitating interoperability with respect to the test of such core-based ICs, especially if they contain cores from different sources. This paper briefly describes IEEE P1500, and illustrates through a simplified example its dual compliance concept, its Scalable Hardware Architecture, and its Core Test Language. This paper provides a preliminary, unapproved view on IEEE P1500. The standard is still under development, and this paper only reflects the view of five active participants of the Standardization Committee on its current status.</description><identifier>ISSN: 1089-3539</identifier><identifier>ISBN: 0780357531</identifier><identifier>ISBN: 9780780357532</identifier><identifier>EISSN: 2378-2250</identifier><identifier>DOI: 10.1109/TEST.1999.805786</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit faults ; Circuit testing ; Crosstalk ; Hardware ; Instruments ; Integrated circuit interconnections ; Manufacturing ; Standardization ; Standards development ; System testing</subject><ispartof>International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), 1999, p.616-627</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/805786$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54555,54920,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/805786$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Marinissen, E.J.</creatorcontrib><creatorcontrib>Zorian, Y.</creatorcontrib><creatorcontrib>Kapur, R.</creatorcontrib><creatorcontrib>Taylor, T.</creatorcontrib><creatorcontrib>Whetsel, L.</creatorcontrib><title>Towards a standard for embedded core test: an example</title><title>International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034)</title><addtitle>TEST</addtitle><description>Integrated circuits are increasingly designed by embedding pre-designed reusable cores. IEEE P1500 Standard for Embedded Core Test (SECT) is a standard-under-development that aims at improving ease of reuse and facilitating interoperability with respect to the test of such core-based ICs, especially if they contain cores from different sources. This paper briefly describes IEEE P1500, and illustrates through a simplified example its dual compliance concept, its Scalable Hardware Architecture, and its Core Test Language. This paper provides a preliminary, unapproved view on IEEE P1500. The standard is still under development, and this paper only reflects the view of five active participants of the Standardization Committee on its current status.</description><subject>Circuit faults</subject><subject>Circuit testing</subject><subject>Crosstalk</subject><subject>Hardware</subject><subject>Instruments</subject><subject>Integrated circuit interconnections</subject><subject>Manufacturing</subject><subject>Standardization</subject><subject>Standards development</subject><subject>System testing</subject><issn>1089-3539</issn><issn>2378-2250</issn><isbn>0780357531</isbn><isbn>9780780357532</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1999</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotj8tqwzAQAEUfUCftvfSkH7Czq7UsqbcS0gcEcojvQZZW4BLHwTK0_fsW0tPMaWCEeESoEMGt2s2-rdA5V1nQxjZXolBkbKmUhmuxAGOBtNGEN6JAsK4kTe5OLHL-BFCgFRRCt-OXn2KWXubZn-KfyzROkoeOY-QowzixnDnPz9KfJH_74Xzke3Gb_DHzwz-XYv-6adfv5Xb39rF-2Za9NXPZKdNQcjFgcCFqSKnhUHPCOqAir1SHSBAMxlRztI12lBJbVJ1PgZiW4ulS7Zn5cJ76wU8_h8sr_QKJbkZH</recordid><startdate>1999</startdate><enddate>1999</enddate><creator>Marinissen, E.J.</creator><creator>Zorian, Y.</creator><creator>Kapur, R.</creator><creator>Taylor, T.</creator><creator>Whetsel, L.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>1999</creationdate><title>Towards a standard for embedded core test: an example</title><author>Marinissen, E.J. ; Zorian, Y. ; Kapur, R. ; Taylor, T. ; Whetsel, L.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i87t-b2763f9dc1c9cd50ff6ec4ef14c123a22b1130c71df4ed86593ffe812bafc3e3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1999</creationdate><topic>Circuit faults</topic><topic>Circuit testing</topic><topic>Crosstalk</topic><topic>Hardware</topic><topic>Instruments</topic><topic>Integrated circuit interconnections</topic><topic>Manufacturing</topic><topic>Standardization</topic><topic>Standards development</topic><topic>System testing</topic><toplevel>online_resources</toplevel><creatorcontrib>Marinissen, E.J.</creatorcontrib><creatorcontrib>Zorian, Y.</creatorcontrib><creatorcontrib>Kapur, R.</creatorcontrib><creatorcontrib>Taylor, T.</creatorcontrib><creatorcontrib>Whetsel, L.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Marinissen, E.J.</au><au>Zorian, Y.</au><au>Kapur, R.</au><au>Taylor, T.</au><au>Whetsel, L.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Towards a standard for embedded core test: an example</atitle><btitle>International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034)</btitle><stitle>TEST</stitle><date>1999</date><risdate>1999</risdate><spage>616</spage><epage>627</epage><pages>616-627</pages><issn>1089-3539</issn><eissn>2378-2250</eissn><isbn>0780357531</isbn><isbn>9780780357532</isbn><abstract>Integrated circuits are increasingly designed by embedding pre-designed reusable cores. IEEE P1500 Standard for Embedded Core Test (SECT) is a standard-under-development that aims at improving ease of reuse and facilitating interoperability with respect to the test of such core-based ICs, especially if they contain cores from different sources. This paper briefly describes IEEE P1500, and illustrates through a simplified example its dual compliance concept, its Scalable Hardware Architecture, and its Core Test Language. This paper provides a preliminary, unapproved view on IEEE P1500. The standard is still under development, and this paper only reflects the view of five active participants of the Standardization Committee on its current status.</abstract><pub>IEEE</pub><doi>10.1109/TEST.1999.805786</doi><tpages>12</tpages></addata></record>
fulltext fulltext_linktorsrc
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ispartof International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), 1999, p.616-627
issn 1089-3539
2378-2250
language eng
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subjects Circuit faults
Circuit testing
Crosstalk
Hardware
Instruments
Integrated circuit interconnections
Manufacturing
Standardization
Standards development
System testing
title Towards a standard for embedded core test: an example
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T05%3A08%3A40IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Towards%20a%20standard%20for%20embedded%20core%20test:%20an%20example&rft.btitle=International%20Test%20Conference%201999.%20Proceedings%20(IEEE%20Cat.%20No.99CH37034)&rft.au=Marinissen,%20E.J.&rft.date=1999&rft.spage=616&rft.epage=627&rft.pages=616-627&rft.issn=1089-3539&rft.eissn=2378-2250&rft.isbn=0780357531&rft.isbn_list=9780780357532&rft_id=info:doi/10.1109/TEST.1999.805786&rft_dat=%3Cieee_CHZPO%3E805786%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i87t-b2763f9dc1c9cd50ff6ec4ef14c123a22b1130c71df4ed86593ffe812bafc3e3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=805786&rfr_iscdi=true