High speed parallel multi-chip interconnection with free space optics

• Main Authors: Xuezhe Zheng, Marchand, P.J., Huang, D., Esener, S.C.
• Format: Conference Proceeding
• Language: English
• Subjects: Assembly systems; Costs; Data communication; Electronics packaging; High speed optical techniques; Manufacturing; Optical arrays; Optical imaging; Optical interconnections; Prototypes
• DOI: 10.1109/PI.1999.806390

In this paper, a high-speed parallel data communication scheme is proposed for multi-chip interconnections. We present the proof of concept and feasibility demonstration of a practical module packaging approach where free-space optical interconnects can be seamlessly integrated on electronic Multi-Chip Modules (MCM) for intra MCM interconnects. Our system level packaging architecture is based on a modified folded 4-f imaging system that has been implemented using only off-the-shelf optics, conventional electronic packaging, as well as passive alignment and assembly techniques to yield a potentially low cost manufacturable packaging solution. The prototype system, as built, supports 48 independent FSOI channels using eight separate laser and detector chips, where each chip consists of a 1D array of 12 devices. All chips are assembled on a single ceramic substrate together with three silicon chips. Parallel opto-electronic free space interconnections have been demonstrated with link speeds of up to 200 MHz per channel. The system is compact at only 10 cubic inches, and scalable as it can easily accommodate additional chips as well as two-dimensional opto-electronic device arrays for increased interconnection density.