Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7

SRAM paves the way for new technology nodes as it is more prone to failure due to intrinsic devices variability and technology process. To further boost high density SRAM yield and performance we need assist techniques and increased SRAM bit cell size at the expense of area. This paper discusses SRA...

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Bibliographic Details
Main Authors: Gupta, Mohit Kumar, Weckx, Pieter, Cosemans, Stefan, Schuddinck, Pieter, Baert, Rogier, Yakimets, Dmitry, Doyoung Jang, Sherazi, Yasser, Raghavan, Praveen, Spessot, Alessio, Mocuta, Anda, Dehaene, Wim
Format: Conference Proceeding
Language:English
Subjects:
beyond N7
Capacitance
CMOS scaling
Delays
FinFETs
Logic gates
memory
Performance evaluation
SRAM
SRAM cells
Online Access:Request full text
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Summary:SRAM paves the way for new technology nodes as it is more prone to failure due to intrinsic devices variability and technology process. To further boost high density SRAM yield and performance we need assist techniques and increased SRAM bit cell size at the expense of area. This paper discusses SRAM design strategies for future technologies nodes like beyond the N7 node, by comparing higher height cells and assist techniques. Although, higher height cells improve variability with scaled nodes but also need assist techniques to lower the operating voltage. Consequently, 122 is shown to meet the yield requirement and the preferred option to use with and without assist circuitry.
ISSN:2378-6558
DOI:10.1109/ESSDERC.2017.8066640