An Innovative Indicator to Evaluate DRAM Cell Transistor Leakage Current Distribution

This paper is the first to propose an innovative method for measuring variations in dynamic random access memory (DRAM) cell transistors. Structural dispersion induces an extremely high cell leakage current, which determines aspects of DRAM performance such as refresh time (tREF). However, no method...

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Bibliographic Details
Published in:IEEE journal of the Electron Devices Society 2018-01, Vol.6, p.494-499
Main Authors: Cho, Min Hee, Jeon, Namho, Kim, Taek Yong, Jeong, Moonyoung, Lee, Sungsam, Hong, Jong Seo, Hong, Hyeong Sun, Yamada, Satoru
Format: Article
Language:English
Subjects:
cell transistor
Current distribution
Current measurement
DRAM
Dynamic random access memory
gate-induced drain leakage current (GIDL)
Indexes
Leakage current
leakage current distribution
Leakage currents
Logic gates
Memory management
process variation
Random access memory
refresh time
retention time
Semiconductor devices
Statistical models
time-fail bit plot (TF slope)
Transistors
Unit cell
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Summary:This paper is the first to propose an innovative method for measuring variations in dynamic random access memory (DRAM) cell transistors. Structural dispersion induces an extremely high cell leakage current, which determines aspects of DRAM performance such as refresh time (tREF). However, no method is currently available for evaluating variations, which is a serious problem in developing DRAM. Although the average leakage current from a test element group has been used as an index for determining cell leakage, it does not provide the distribution of unit cell leakage current. We find that cell leakage distribution can be calculated from the slope of the retention time-fail bit plot (defined as TF slope). A steep slope indicates a narrow cell leakage distribution, which corresponds to a narrower structural distribution, and therefore a long tREF. Using statistical models and experiments based on extensive data, our results confirm this relationship. Another impact and contribution of TF slope are that the development period can be saved because a wrong decision (which process is better) can be avoided. This method is used successfully as an indicator to estimate selected processes and to facilitate DRAM development.
ISSN:2168-6734
2168-6734
DOI:10.1109/JEDS.2017.2758026