Performance Characterization and Design Guidelines for Efficient Processor–FPGA Communication in Cyclone V FPSoCs

• Published in: IEEE transactions on industrial electronics (1982) 2018-05, Vol.65 (5), p.4368-4377
• Main Authors: Molanes, Roberto Fernandez, Rodriguez-Andina, Juan J., Farina, Jose
• Format: Article
• Language: English
• Subjects: Cyclones; Design; Design guidelines; Designers; Devices; Fabrics; Field programmable gate arrays; field-program-mable system-on-chip (FPSoC); FPGA; Guidelines; Hardware; Hardware design languages; Industrial electronics; Microprocessors; performance characterization; Performance evaluation; Processors; processor–FPGA communications; Program processors; System on chip
• ISSN: 0278-0046; 1557-9948
• DOI: 10.1109/TIE.2017.2766581

Field programmable systems-on-chip (FPS-oCs) are heterogeneous reconfigurable platforms consisting of hard processors and FPGA fabric. They provide software designers with an efficient way to accelerate the execution of their algorithms and hardware designers with much more high-level processing power than that provided by soft-cores implemented in standard logic FPGA resources. Despite these very useful characteristics, the penetration of FPSoCs in digital designs for industrial electronics applications is very limited. There is a general agreement among researchers in the area that one of the main reasons for this is the lack of knowledge about the best way to interconnect the processors and the FPGA fabric in these devices. To address this issue, this paper presents an extensive characterization and analysis of processor-FPGA communications in a widely used family of FPSoCs, namely Cyclone V devices. To the best of authors´ knowledge, this is the most complete study of FPSoCs devices in this regard to date. From the experiments conducted and the results obtained, a set of design guidelines are introduced to help FPSoC designers take the most possible advantage of the excellent characteristics of these devices.