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A bandgap voltage reference using digital CMOS process
This work describes some issues and criteria for the design of a bandgap voltage reference. It examines a particular voltage reference architecture, characteristics of the operational amplifier, parasitic bipolar transistor biasing currents and the start-up circuit. Test circuits have been fabricate...
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Main Authors: | , , , , |
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Format: | Conference Proceeding |
Language: | English |
Subjects: | |
Online Access: | Request full text |
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Summary: | This work describes some issues and criteria for the design of a bandgap voltage reference. It examines a particular voltage reference architecture, characteristics of the operational amplifier, parasitic bipolar transistor biasing currents and the start-up circuit. Test circuits have been fabricated in the AMS 0.8 /spl mu/m n-well CMOS process. Experimental results yield an output voltage which is constant within 0.72% over the temperature range of -40/spl deg/C to 95/spl deg/C and the power supply range of 5 V/spl plusmn/10%. |
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DOI: | 10.1109/ICECS.1998.814886 |