Lower power Viterbi decoder architecture with a new clock-gating trace-back unit

This paper presents a new algorithm on lower-power survivor path memory implementation of the trace-back systolic array Viterbi algorithm. A novel idea is to reuse the already-generated trace-back routes to reduce the number of trace-back operations. It results in increasing the area of spurious swi...

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Bibliographic Details
Main Authors: Je Hyuk Ryu, Sang Cheon Kim, Jun Dong Cho, Hyun Woo Park, Yung Hoon Chang
Format: Conference Proceeding
Language:English
Subjects:
Channel coding
Clocks
Convolution
Convolutional codes
Decoding
Digital communication
Registers
Signal processing algorithms
Systolic arrays
Viterbi algorithm
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Summary:This paper presents a new algorithm on lower-power survivor path memory implementation of the trace-back systolic array Viterbi algorithm. A novel idea is to reuse the already-generated trace-back routes to reduce the number of trace-back operations. It results in increasing the area of spurious switching activity region, and further reducing the switching activity with gated-clocks during trace-back operation. With the SYNOPSYS power estimation tool, DesignPower, our experimental result shows on the average 40% reduction in power with the same latency at a cost of 23% increase in area against the trace-back unit introduced by Truong et al. (1992). The proposed survivor memory scheme can be applied to the digital communication systems for targeting low power consumption.
DOI:10.1109/ICVC.1999.820910