Energy-efficient wireless interconnection framework for multichip systems with in-package memory stacks

Multichip systems with memory stacks and various processing chips are at the heart of platform based designs such as servers and embedded systems. Full utilization of the benefits of these integrated multichip systems need a seamless, and scalable in-package interconnection framework. However, state...

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Bibliographic Details
Main Authors: Shamim, Md Shahriar, Ahmed, M. Meraj, Mansoor, Naseef, Ganguly, Amlan
Format: Conference Proceeding
Language:English
Subjects:
Bandwidth
Energy efficiency
Multichip
Multicore processing
Network-on-Chip
Switches
System-on-chip
Transceivers
Wireless communication
Wireless Interconnect
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Description
Summary:Multichip systems with memory stacks and various processing chips are at the heart of platform based designs such as servers and embedded systems. Full utilization of the benefits of these integrated multichip systems need a seamless, and scalable in-package interconnection framework. However, state-of-the-art inter-chip communication requires long wireline channels which increases energy consumption and latency while decreasing data bandwidth. Here, we propose the design of an energy-efficient, seamless wireless interconnection network for multichip systems. We demonstrate with cycle-accurate simulations that such a design reduces the energy consumption and latency while increasing the bandwidth in comparison to modern multichip integration systems.
ISSN:2164-1706
DOI:10.1109/SOCC.2017.8226077