A proposed reliable and power efficient 14T full adder circuit design

This paper presents design of a new stable 14T full power efficient adder circuit. The proposed circuit is designed based on Pass Transistor Logic (PTL) network using NMOS transistor only. The proposed circuit is simulated at layout level using Microwind EDA tools for 45nm technology in terms of pow...

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Bibliographic Details
Main Authors: Subramaniam, Shahmini, Wilson, Tan Wee Xin, Singh, Ajay Kumar, Murthy, Gajula Ramana
Format: Conference Proceeding
Language:English
Subjects:
14T full adder
Adders
Conferences
delay
IEEE Regions
Layout
leakage current
Logic gates
NMOS
Pass Transistor Logic (PTL)
power delay product
Power demand
power dissipation
Transistors
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Description
Summary:This paper presents design of a new stable 14T full power efficient adder circuit. The proposed circuit is designed based on Pass Transistor Logic (PTL) network using NMOS transistor only. The proposed circuit is simulated at layout level using Microwind EDA tools for 45nm technology in terms of power and voltage level at the sum and carry nodes. The proposed circuit performance is compared with a similar 14T adder circuits and found the proposed adder circuit consumes lower power due to smaller load capacitance and parasitic resistance. The logic level at the sum and carry nodes maintains at strong 1 or strong 0 due to proposed circuit's design architecture.
ISSN:2159-3450
DOI:10.1109/TENCON.2017.8227834