A 6LoWPAN Accelerator for Internet of Things Endpoint Devices

The Internet of Things (IoT) is revolutionizing the Internet of the future and the way smart devices, people, and processes interact with each other. Challenges in endpoint devices (EDs) communication are due not only to the security and privacy-related requirements but also due to the ever-growing...

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Bibliographic Details
Published in:IEEE internet of things journal 2018-02, Vol.5 (1), p.371-377
Main Authors: Gomes, Tiago, Salgado, Filipe, Pinto, Sandro, Cabral, Jorge, Tavares, Adriano
Format: Article
Language:English
Subjects:
Constrained devices
Electronic devices
Energy consumption
Field programmable gate arrays
field-programmable gate array (FPGA)
Filtration
IEEE 802.15 Standard
IEEE 802.15.4
Internet of Things
Internet of Things (IoT)
IP (Internet Protocol)
IPv6 over low power wireless personal area networks (6LoWPAN)
Microcontrollers
network accelerator
Performance evaluation
Protocols
Radio transceivers
Resource utilization
system-on-chip (SoC)
Wireless networks
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Summary:The Internet of Things (IoT) is revolutionizing the Internet of the future and the way smart devices, people, and processes interact with each other. Challenges in endpoint devices (EDs) communication are due not only to the security and privacy-related requirements but also due to the ever-growing amount of data transferred over the network that needs to be handled, which can considerably reduce the system availability to perform other tasks. This paper presents an IPv6 over low power wireless personal area networks (6LoWPAN) accelerator for the IP-based IoT networks, which is able to process and filter IPv6 packets received by an IEEE 802.15.4 radio transceiver without interrupting the microcontroller. It offers nearly 13.24% of performance overhead reduction for the packet processing and the address filtering tasks, while guaranteeing full system availability when unwanted packets are received and discarded. The contribution is meant to be deployed on heterogeneous EDs at the network edge, which include on the same architecture, field-programmable gate array (FPGA) technology beside a microcontroller and an IEEE 802.15.4-compliant radio transceiver. Performed evaluations include the low FPGA hardware resources utilization and the energy consumption analysis when the processing and accepting/rejection of a received packet is performed by the 6LoWPAN accelerator.
ISSN:2327-4662
2327-4662
DOI:10.1109/JIOT.2017.2785659