High quality ultra-thin (1.5 nm) TiO/sub 2/-Si/sub 3/N/sub 4/ gate dielectric for deep sub-micron CMOS technology

This paper presents the physical and electrical properties of ultra-thin (/spl sim/1.5 nm EOT) TiO/sub 2//Si/sub 3/N/sub 4/ gate dielectrics fabricated by the jet-vapor deposition (JVD) process for both n- and p-channel field-effect transistors. It will be shown that the use of TiO/sub 2//Si/sub 3/N...

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Bibliographic Details
Main Authors: Xin Guo, Xiewen Wang, Zhijiong Luo, Ma, T.P., Tamagawa, T.
Format: Conference Proceeding
Language:English
Subjects:
Annealing
CMOS technology
Crystallization
Degradation
Dielectric materials
High K dielectric materials
High-K gate dielectrics
Leakage current
MOSFET circuits
Temperature
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Summary:This paper presents the physical and electrical properties of ultra-thin (/spl sim/1.5 nm EOT) TiO/sub 2//Si/sub 3/N/sub 4/ gate dielectrics fabricated by the jet-vapor deposition (JVD) process for both n- and p-channel field-effect transistors. It will be shown that the use of TiO/sub 2//Si/sub 3/N/sub 4/ to replace SiO/sub 2/ as gate dielectric can reduce the gate leakage current by several orders of magnitude while maintaining excellent interface quality, high reliability, low trap density, and competitive n-and p-channel MOSFET performance.
DOI:10.1109/IEDM.1999.823864