A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2018-04, Vol.26 (4), p.756-767
• Main Authors: Liu, Qiyuan, Edward, Alexander, Zhou, Dadian, Silva-Martinez, Jose
• Format: Article
• Language: English
• Subjects: Analog-to-digital converter; Delays; delta–sigma modulator (ΔΣM); finite impulse response (FIR); Finite impulse response filters; Jitter; loop-unrolling; Modulation; Multi-stage noise shaping; multistage noise shaping (MASH); Quantization (signal); Transfer functions
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2017.2780272

This paper presents a continuous-time multistage noise-shaping (MASH) delta-sigma modulator (CT- \Delta \Sigma \text{M} ) employing finite impulse response (FIR) digital-to-analog converters (DACs) and encoder-embedded loop-unrolling (EELU) quantizers. The proposed MASH 1-1-1 topology is a cascade of three single-loop first-order CT- \Delta \Sigma \text{M} stages, each of which consists of an active RC integrator, a current-steering DAC, and an EELU quantizer. An FIR filter in the main 1.5-bit DAC improves the modulator's jitter sensitivity performance. FIR's effect on the noise transfer function of the modulator is compensated in the digital domain, thanks to the MASH topology. Instead of employing a conventional analog direct feedback path for excess loop delay compensation, a 1.5-bit EELU quantizer based on multiplexing comparator outputs is proposed; this approach is suitable for high-speed operation. Fabricated in a 40-nm low-power CMOS technology, the modulator's prototype achieves a 67.3 dB of signal-to-noise-and-distortion ratio, 68 dB of signal-to-noise ratio, and 68.2 dB of dynamic range within 50.5 MHz of bandwidth, while consuming 19 mW of total power.