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Leak Point Locating in Hardware Implementations of Higher-Order Masking Schemes
Secure masking schemes have been proven in theory to be secure countermeasures against side-channel attacks. The security framework proposed by Ishai, Sahai, and Wagner, known as the Ishai-Sahai-Wagner scheme, is one of the most acceptable secure models of the existing d th-order masking schemes, w...
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Published in: | IEEE transactions on computer-aided design of integrated circuits and systems 2018-12, Vol.37 (12), p.3008-3019 |
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description | Secure masking schemes have been proven in theory to be secure countermeasures against side-channel attacks. The security framework proposed by Ishai, Sahai, and Wagner, known as the Ishai-Sahai-Wagner scheme, is one of the most acceptable secure models of the existing d th-order masking schemes, where d represents the masking order and plays the role of a security parameter. However, a gap may exist between scheme and design. Several analyses have determined that the glitch has been regarded as the main challenge of masking in hardware designs. A practical method of locating the precise position of leakage points (LPs) in the original hardware design is very rare. Existing research on this glitch mainly focuses on the first-order leakages; however, higher-order analysis can combine several shares to recover the secret key. In this paper, we propose a practical method, sensitive glitch location (SGL) method to locate the less order leakage in hardware design. Specifically, the SGL method can locate any-order of LP in the hardware implementation of d th-order masking schemes. We conducted experiments and verified that the time complexity of SGL on the d th-order masking schemes is {O(nm)} , where m is the number of signals and n is the number of shares in masking scheme. It can therefore be regarded as an efficient tool for the masking designs. In addition, we analyzed the d th-order masking scheme proposed by Rivain and Prouff (2010) along with the SecMult algorithm from the Rivain-Prouff countermeasure, which has been analyzed by our SGL. The experimental results verified that a higher-order leakage may exist in certain hardware designs, even the masking scheme has been proven as a secure countermeasure. To the best of our knowledge, SGL is the first tool that can be used to locate any-order of power/electromagnetic LP in hardware designs. It thus shows the weakness in the original desig |
doi_str_mv | 10.1109/TCAD.2018.2789727 |
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The security framework proposed by Ishai, Sahai, and Wagner, known as the Ishai-Sahai-Wagner scheme, is one of the most acceptable secure models of the existing <inline-formula> <tex-math notation="LaTeX">d </tex-math></inline-formula>th-order masking schemes, where <inline-formula> <tex-math notation="LaTeX">d </tex-math></inline-formula> represents the masking order and plays the role of a security parameter. However, a gap may exist between scheme and design. Several analyses have determined that the glitch has been regarded as the main challenge of masking in hardware designs. A practical method of locating the precise position of leakage points (LPs) in the original hardware design is very rare. Existing research on this glitch mainly focuses on the first-order leakages; however, higher-order analysis can combine several shares to recover the secret key. In this paper, we propose a practical method, sensitive glitch location (SGL) method to locate the less order leakage in hardware design. Specifically, the SGL method can locate any-order of LP in the hardware implementation of <inline-formula> <tex-math notation="LaTeX">d </tex-math></inline-formula>th-order masking schemes. We conducted experiments and verified that the time complexity of SGL on the <inline-formula> <tex-math notation="LaTeX">d </tex-math></inline-formula>th-order masking schemes is <inline-formula> <tex-math notation="LaTeX">{O(nm)} </tex-math></inline-formula>, where <inline-formula> <tex-math notation="LaTeX">m </tex-math></inline-formula> is the number of signals and <inline-formula> <tex-math notation="LaTeX">n </tex-math></inline-formula> is the number of shares in masking scheme. It can therefore be regarded as an efficient tool for the masking designs. In addition, we analyzed the <inline-formula> <tex-math notation="LaTeX">d </tex-math></inline-formula>th-order masking scheme proposed by Rivain and Prouff (2010) along with the SecMult algorithm from the Rivain-Prouff countermeasure, which has been analyzed by our SGL. The experimental results verified that a higher-order leakage may exist in certain hardware designs, even the masking scheme has been proven as a secure countermeasure. To the best of our knowledge, SGL is the first tool that can be used to locate any-order of power/electromagnetic LP in hardware designs. It thus shows the weakness in the original design file of hardware implementations. This property can help designers directly improve the real security of the designs. Moreover, SGL returns the path of the leakages, which can elucidate the original cause and propagation of the weakness.]]></description><identifier>ISSN: 0278-0070</identifier><identifier>EISSN: 1937-4151</identifier><identifier>DOI: 10.1109/TCAD.2018.2789727</identifier><identifier>CODEN: ITCSDI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject><italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">d th-order masking schemes ; Algorithm design and analysis ; Design ; Electronic mail ; field-programmable gate array (FPGA) ; Hardware ; hardware implementation ; Integrated circuit modeling ; Leakage ; Masking ; practical security ; Security ; Semiconductor device modeling ; side-channel attack (SCA)</subject><ispartof>IEEE transactions on computer-aided design of integrated circuits and systems, 2018-12, Vol.37 (12), p.3008-3019</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2018</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c293t-c803f94682e1dad97603bd357e414d0c4d8ee47baf069060abf2939fd9a000853</citedby><cites>FETCH-LOGICAL-c293t-c803f94682e1dad97603bd357e414d0c4d8ee47baf069060abf2939fd9a000853</cites><orcidid>0000-0001-7151-9270 ; 0000-0003-2218-0164 ; 0000-0003-0492-3278</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8246545$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,27924,27925,54796</link.rule.ids></links><search><creatorcontrib>Ming, Tang</creatorcontrib><creatorcontrib>Yanbin, Li</creatorcontrib><creatorcontrib>Dongyan, Zhao</creatorcontrib><creatorcontrib>Yuguang, Li</creatorcontrib><creatorcontrib>Fei, Yan</creatorcontrib><creatorcontrib>Huanguo, Zhang</creatorcontrib><title>Leak Point Locating in Hardware Implementations of Higher-Order Masking Schemes</title><title>IEEE transactions on computer-aided design of integrated circuits and systems</title><addtitle>TCAD</addtitle><description><![CDATA[Secure masking schemes have been proven in theory to be secure countermeasures against side-channel attacks. The security framework proposed by Ishai, Sahai, and Wagner, known as the Ishai-Sahai-Wagner scheme, is one of the most acceptable secure models of the existing <inline-formula> <tex-math notation="LaTeX">d </tex-math></inline-formula>th-order masking schemes, where <inline-formula> <tex-math notation="LaTeX">d </tex-math></inline-formula> represents the masking order and plays the role of a security parameter. However, a gap may exist between scheme and design. Several analyses have determined that the glitch has been regarded as the main challenge of masking in hardware designs. A practical method of locating the precise position of leakage points (LPs) in the original hardware design is very rare. Existing research on this glitch mainly focuses on the first-order leakages; however, higher-order analysis can combine several shares to recover the secret key. In this paper, we propose a practical method, sensitive glitch location (SGL) method to locate the less order leakage in hardware design. Specifically, the SGL method can locate any-order of LP in the hardware implementation of <inline-formula> <tex-math notation="LaTeX">d </tex-math></inline-formula>th-order masking schemes. We conducted experiments and verified that the time complexity of SGL on the <inline-formula> <tex-math notation="LaTeX">d </tex-math></inline-formula>th-order masking schemes is <inline-formula> <tex-math notation="LaTeX">{O(nm)} </tex-math></inline-formula>, where <inline-formula> <tex-math notation="LaTeX">m </tex-math></inline-formula> is the number of signals and <inline-formula> <tex-math notation="LaTeX">n </tex-math></inline-formula> is the number of shares in masking scheme. It can therefore be regarded as an efficient tool for the masking designs. In addition, we analyzed the <inline-formula> <tex-math notation="LaTeX">d </tex-math></inline-formula>th-order masking scheme proposed by Rivain and Prouff (2010) along with the SecMult algorithm from the Rivain-Prouff countermeasure, which has been analyzed by our SGL. The experimental results verified that a higher-order leakage may exist in certain hardware designs, even the masking scheme has been proven as a secure countermeasure. To the best of our knowledge, SGL is the first tool that can be used to locate any-order of power/electromagnetic LP in hardware designs. It thus shows the weakness in the original design file of hardware implementations. This property can help designers directly improve the real security of the designs. Moreover, SGL returns the path of the leakages, which can elucidate the original cause and propagation of the weakness.]]></description><subject><italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">d th-order masking schemes</subject><subject>Algorithm design and analysis</subject><subject>Design</subject><subject>Electronic mail</subject><subject>field-programmable gate array (FPGA)</subject><subject>Hardware</subject><subject>hardware implementation</subject><subject>Integrated circuit modeling</subject><subject>Leakage</subject><subject>Masking</subject><subject>practical security</subject><subject>Security</subject><subject>Semiconductor device modeling</subject><subject>side-channel attack (SCA)</subject><issn>0278-0070</issn><issn>1937-4151</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2018</creationdate><recordtype>article</recordtype><recordid>eNo9kFtLwzAUgIMoOKc_QHwJ-Nx5cmmTPI552aAywfkcsuZ06y7tTDrEf2_Lhk-Bk-87Bz5C7hmMGAPztJiMn0ccmB5xpY3i6oIMmBEqkSxll2QA3TgBUHBNbmLcADCZcjMg8xzdln40Vd3SvClcW9UrWtV06oL_cQHpbH_Y4R7rtvtq6kibkk6r1RpDMg8eA313cds7n8W6w-ItuSrdLuLd-R2Sr9eXxWSa5PO32WScJwU3ok0KDaI0MtMcmXfeqAzE0otUoWTSQyG9RpRq6UrIDGTglmXnmdIbBwA6FUPyeNp7CM33EWNrN80x1N1Jy5lQqc6EUR3FTlQRmhgDlvYQqr0Lv5aB7bvZvpvtu9lzt855ODkVIv7zmssslan4A-6FaFc</recordid><startdate>20181201</startdate><enddate>20181201</enddate><creator>Ming, Tang</creator><creator>Yanbin, Li</creator><creator>Dongyan, Zhao</creator><creator>Yuguang, Li</creator><creator>Fei, Yan</creator><creator>Huanguo, Zhang</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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The security framework proposed by Ishai, Sahai, and Wagner, known as the Ishai-Sahai-Wagner scheme, is one of the most acceptable secure models of the existing <inline-formula> <tex-math notation="LaTeX">d </tex-math></inline-formula>th-order masking schemes, where <inline-formula> <tex-math notation="LaTeX">d </tex-math></inline-formula> represents the masking order and plays the role of a security parameter. However, a gap may exist between scheme and design. Several analyses have determined that the glitch has been regarded as the main challenge of masking in hardware designs. A practical method of locating the precise position of leakage points (LPs) in the original hardware design is very rare. Existing research on this glitch mainly focuses on the first-order leakages; however, higher-order analysis can combine several shares to recover the secret key. In this paper, we propose a practical method, sensitive glitch location (SGL) method to locate the less order leakage in hardware design. Specifically, the SGL method can locate any-order of LP in the hardware implementation of <inline-formula> <tex-math notation="LaTeX">d </tex-math></inline-formula>th-order masking schemes. We conducted experiments and verified that the time complexity of SGL on the <inline-formula> <tex-math notation="LaTeX">d </tex-math></inline-formula>th-order masking schemes is <inline-formula> <tex-math notation="LaTeX">{O(nm)} </tex-math></inline-formula>, where <inline-formula> <tex-math notation="LaTeX">m </tex-math></inline-formula> is the number of signals and <inline-formula> <tex-math notation="LaTeX">n </tex-math></inline-formula> is the number of shares in masking scheme. It can therefore be regarded as an efficient tool for the masking designs. In addition, we analyzed the <inline-formula> <tex-math notation="LaTeX">d </tex-math></inline-formula>th-order masking scheme proposed by Rivain and Prouff (2010) along with the SecMult algorithm from the Rivain-Prouff countermeasure, which has been analyzed by our SGL. The experimental results verified that a higher-order leakage may exist in certain hardware designs, even the masking scheme has been proven as a secure countermeasure. To the best of our knowledge, SGL is the first tool that can be used to locate any-order of power/electromagnetic LP in hardware designs. It thus shows the weakness in the original design file of hardware implementations. This property can help designers directly improve the real security of the designs. Moreover, SGL returns the path of the leakages, which can elucidate the original cause and propagation of the weakness.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCAD.2018.2789727</doi><tpages>12</tpages><orcidid>https://orcid.org/0000-0001-7151-9270</orcidid><orcidid>https://orcid.org/0000-0003-2218-0164</orcidid><orcidid>https://orcid.org/0000-0003-0492-3278</orcidid></addata></record> |
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subjects | <italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">d th-order masking schemes Algorithm design and analysis Design Electronic mail field-programmable gate array (FPGA) Hardware hardware implementation Integrated circuit modeling Leakage Masking practical security Security Semiconductor device modeling side-channel attack (SCA) |
title | Leak Point Locating in Hardware Implementations of Higher-Order Masking Schemes |
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